Front-end readout system for PHENIX RICH

Y. Tanaka, H. Hara, K. Ebisu, M. Hibino, T. Matsumoto, J. Kikuchi, A. L. Wintenberg, J. W. Walker, S. Frank, C. Moscone, J. P. Jones, G. R. Young, K. Oyama, H. Hamagaki

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, source synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with 128-bits data bus. Total transaction time is estimated to be less than 30μs per event when this system is applied for the experiment. This result indicates that the performance is satisfied with the requirement of the PHENIX experiment.

    Original languageEnglish
    Title of host publicationIEEE Nuclear Science Symposium and Medical Imaging Conference
    PublisherIEEE
    Pages346-352
    Number of pages7
    ISBN (Print)0780350227
    StatePublished - 1999
    EventProceedings of the 1998 IEEE Nuclear Science Symposium Conference Record - Toronto, Que, Can
    Duration: Nov 8 1998Nov 14 1998

    Publication series

    NameIEEE Nuclear Science Symposium and Medical Imaging Conference
    Volume1

    Conference

    ConferenceProceedings of the 1998 IEEE Nuclear Science Symposium Conference Record
    CityToronto, Que, Can
    Period11/8/9811/14/98

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