Abstract
A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, source synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with 128-bits data bus. Total transaction time is estimated to be less than 30μs per event when this system is applied for the experiment. This result indicates that the performance is satisfied with the requirement of the PHENIX experiment.
Original language | English |
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Title of host publication | IEEE Nuclear Science Symposium and Medical Imaging Conference |
Publisher | IEEE |
Pages | 346-352 |
Number of pages | 7 |
ISBN (Print) | 0780350227 |
State | Published - 1999 |
Event | Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record - Toronto, Que, Can Duration: Nov 8 1998 → Nov 14 1998 |
Publication series
Name | IEEE Nuclear Science Symposium and Medical Imaging Conference |
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Volume | 1 |
Conference
Conference | Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record |
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City | Toronto, Que, Can |
Period | 11/8/98 → 11/14/98 |