Front-end readout system for PHENIX RICH

Y. Tanaka; H. Hara; K. Ebisu; M. Hibino; T. Matsumoto; T. Sakaguchi; J. Kikuchi; A. L. Wintenberg; J. W. Walker; S. Frank; C. Moscone; J. P. Jones; G. R. Young; K. Oyama; H. Hamagaki

doi:10.1109/23.903835

Front-end readout system for PHENIX RICH

Y. Tanaka, H. Hara, K. Ebisu, M. Hibino, T. Matsumoto, T. Sakaguchi, J. Kikuchi, A. L. Wintenberg, J. W. Walker, S. Frank, C. Moscone, J. P. Jones, G. R. Young, K. Oyama, H. Hamagaki

Sensors and Electronics

Research output: Contribution to journal › Article › peer-review

Abstract

A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment.

Original language	English
Pages (from-to)	1995-2002
Number of pages	8
Journal	IEEE Transactions on Nuclear Science
Volume	47
Issue number	6
DOIs	https://doi.org/10.1109/23.903835
State	Published - Dec 2000

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title = "Front-end readout system for PHENIX RICH",

abstract = "A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment.",

author = "Y. Tanaka and H. Hara and K. Ebisu and M. Hibino and T. Matsumoto and T. Sakaguchi and J. Kikuchi and Wintenberg, {A. L.} and Walker, {J. W.} and S. Frank and C. Moscone and Jones, {J. P.} and Young, {G. R.} and K. Oyama and H. Hamagaki",

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TY - JOUR

T1 - Front-end readout system for PHENIX RICH

AU - Tanaka, Y.

AU - Hara, H.

AU - Ebisu, K.

AU - Hibino, M.

AU - Matsumoto, T.

AU - Sakaguchi, T.

AU - Kikuchi, J.

AU - Wintenberg, A. L.

AU - Walker, J. W.

AU - Frank, S.

AU - Moscone, C.

AU - Jones, J. P.

AU - Young, G. R.

AU - Oyama, K.

AU - Hamagaki, H.

PY - 2000/12

Y1 - 2000/12

N2 - A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment.

AB - A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment.

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VL - 47

SP - 1995

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JO - IEEE Transactions on Nuclear Science

JF - IEEE Transactions on Nuclear Science

IS - 6

ER -

Front-end readout system for PHENIX RICH

Abstract

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