Flicker noise behavior of MOSFETs fabricated in 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion

M. N. Ericson; C. L. Britton; J. M. Rochelle; B. J. Blalock; D. M. Binkley; A. L. Wintenberg; B. D. Williamson

doi:10.1109/TNS.2003.815146

Flicker noise behavior of MOSFETs fabricated in 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion

M. N. Ericson, C. L. Britton, J. M. Rochelle, B. J. Blalock, D. M. Binkley, A. L. Wintenberg, B. D. Williamson

Sensors and Electronics

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Abstract

This paper presents a summary of the measured noise behavior of CMOS MOSFET's fabricated in the Peregrine 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device flicker noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum flicker noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.

Original language	English
Pages (from-to)	963-968
Number of pages	6
Journal	IEEE Transactions on Nuclear Science
Volume	50
Issue number	4 II
DOIs	https://doi.org/10.1109/TNS.2003.815146
State	Published - Aug 2003

Funding

Manuscript received July 5, 2002; revised July 15, 2003. This research was supported by the U.S. Department of Energy and performed at Oak Ridge National Laboratory, managed by UT-Battelle for the U.S. Department of Energy under Contract DE-AC05-00OR22725. M. N. Ericson, C. L. Britton, Jr., and A. L. Wintenberg are with the Oak Ridge National Laboratory, Oak Ridge, TN 38731 USA (e-mail: [email protected]; [email protected]; [email protected]). J. M. Rochelle is with Concorde Microsystems, Inc., Knoxville, TN 37932 USA (e-mail: [email protected]). B. J. Blalock and B. D. Williamson are with the University of Tennessee, Knoxville, TN 37966 USA (e-mail: [email protected]; [email protected]). D. M. Binkley is with the University of North Carolina, Charlotte, NC 28223 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TNS.2003.815146

Keywords

CMOSFETs
Flicker noise
Inversion coefficient
Noise measurement
Silicon on insulator technology

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Ericson, M. N., Britton, C. L., Rochelle, J. M., Blalock, B. J., Binkley, D. M., Wintenberg, A. L., & Williamson, B. D. (2003). Flicker noise behavior of MOSFETs fabricated in 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion. IEEE Transactions on Nuclear Science, 50(4 II), 963-968. https://doi.org/10.1109/TNS.2003.815146

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abstract = "This paper presents a summary of the measured noise behavior of CMOS MOSFET's fabricated in the Peregrine 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device flicker noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum flicker noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.",

keywords = "CMOSFETs, Flicker noise, Inversion coefficient, Noise measurement, Silicon on insulator technology",

author = "Ericson, {M. N.} and Britton, {C. L.} and Rochelle, {J. M.} and Blalock, {B. J.} and Binkley, {D. M.} and Wintenberg, {A. L.} and Williamson, {B. D.}",

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AU - Ericson, M. N.

AU - Britton, C. L.

AU - Rochelle, J. M.

AU - Blalock, B. J.

AU - Binkley, D. M.

AU - Wintenberg, A. L.

AU - Williamson, B. D.

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N2 - This paper presents a summary of the measured noise behavior of CMOS MOSFET's fabricated in the Peregrine 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device flicker noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum flicker noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.

AB - This paper presents a summary of the measured noise behavior of CMOS MOSFET's fabricated in the Peregrine 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device flicker noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum flicker noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.

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Flicker noise behavior of MOSFETs fabricated in 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion

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