TY - GEN
T1 - FLAME
T2 - 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
AU - Belviranli, Mehmet E.
AU - Vetter, Jeffrey S.
N1 - Publisher Copyright:
© 2019 EDAA.
PY - 2019/5/14
Y1 - 2019/5/14
N2 - The slowdown of Moore's law has caused an escalation in architectural diversity over the last decade, and agile development of domain-specific heterogeneous chips is becoming a high priority. However, this agile development must also consider portable programming environments and other architectural constraints in the system design. More importantly, understanding the role of each component in an end-to-end system design is important to both architects and application developers and must include metrics like power, performance, space, cost, and reliability. Being able to quickly and precisely characterize the needs of an application in the early stages of hardware design is an essential step toward converging on the primary components of these increasingly heterogeneous platforms. In this paper, we introduce FLAME, a graph-based machine representation to flexibly model a given hardware design at any desired resolution while providing the ability to refine specific components along the hierarchy. FLAME allows each processing unit in the system to declare its specific capabilities and enables higher level elements to reuse and leverage these declarations to form more complex system topologies. Applications are characterized with the Aspen application model; each component has the ability to report its characteristic behavior for a given application model against a supported metric. We demonstrate the feasibility of FLAME for several workloads via multi-core machine representations on different levels abstraction.
AB - The slowdown of Moore's law has caused an escalation in architectural diversity over the last decade, and agile development of domain-specific heterogeneous chips is becoming a high priority. However, this agile development must also consider portable programming environments and other architectural constraints in the system design. More importantly, understanding the role of each component in an end-to-end system design is important to both architects and application developers and must include metrics like power, performance, space, cost, and reliability. Being able to quickly and precisely characterize the needs of an application in the early stages of hardware design is an essential step toward converging on the primary components of these increasingly heterogeneous platforms. In this paper, we introduce FLAME, a graph-based machine representation to flexibly model a given hardware design at any desired resolution while providing the ability to refine specific components along the hierarchy. FLAME allows each processing unit in the system to declare its specific capabilities and enables higher level elements to reuse and leverage these declarations to form more complex system topologies. Applications are characterized with the Aspen application model; each component has the ability to report its characteristic behavior for a given application model against a supported metric. We demonstrate the feasibility of FLAME for several workloads via multi-core machine representations on different levels abstraction.
UR - http://www.scopus.com/inward/record.url?scp=85068408245&partnerID=8YFLogxK
U2 - 10.23919/DATE.2019.8747521
DO - 10.23919/DATE.2019.8747521
M3 - Conference contribution
AN - SCOPUS:85068408245
T3 - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
SP - 1775
EP - 1780
BT - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 25 March 2019 through 29 March 2019
ER -