FLAME: Graph-based hardware representations for rapid and precise performance modeling

Mehmet E. Belviranli, Jeffrey S. Vetter

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

The slowdown of Moore's law has caused an escalation in architectural diversity over the last decade, and agile development of domain-specific heterogeneous chips is becoming a high priority. However, this agile development must also consider portable programming environments and other architectural constraints in the system design. More importantly, understanding the role of each component in an end-to-end system design is important to both architects and application developers and must include metrics like power, performance, space, cost, and reliability. Being able to quickly and precisely characterize the needs of an application in the early stages of hardware design is an essential step toward converging on the primary components of these increasingly heterogeneous platforms. In this paper, we introduce FLAME, a graph-based machine representation to flexibly model a given hardware design at any desired resolution while providing the ability to refine specific components along the hierarchy. FLAME allows each processing unit in the system to declare its specific capabilities and enables higher level elements to reuse and leverage these declarations to form more complex system topologies. Applications are characterized with the Aspen application model; each component has the ability to report its characteristic behavior for a given application model against a supported metric. We demonstrate the feasibility of FLAME for several workloads via multi-core machine representations on different levels abstraction.

Original languageEnglish
Title of host publicationProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1775-1780
Number of pages6
ISBN (Electronic)9783981926323
DOIs
StatePublished - May 14 2019
Event22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 - Florence, Italy
Duration: Mar 25 2019Mar 29 2019

Publication series

NameProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Volume2019-January

Conference

Conference22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Country/TerritoryItaly
CityFlorence
Period03/25/1903/29/19

Funding

ACKNOWLEDGMENTS This work was supported by DARPA MTO DSSOC project 1868-Z203-18, and the Exascale Computing Project (17-SC-20-SC), a collaborative effort of the U.S. Department of Energy Office of Science and the National Nuclear Security Administration This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains estimations for the matmul kernel using models created with FLAME. As the arithmetic intensity increases with larger input sizes, the throughput is bottlenecked by the computational limits.

FundersFunder number
U.S. Department of Energy Office of Science
US Department of Energy
U.S. Department of Energy
Defense Advanced Research Projects Agency17-SC-20-SC, 1868-Z203-18
National Nuclear Security AdministrationDE-AC05-00OR22725

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