Abstract
This chapter discusses application usage of the "reserved" core on an Intel Xeon Phi coprocessor through an examination of multiple thread placement strategies. In doing so, this chapter also seeks to extend discussion on less conventional thread management techniques when using a centralized scheduler model, and look at the interoperability of MPI and PThreads.
| Original language | English |
|---|---|
| Title of host publication | High Performance Parallelism Pearls |
| Subtitle of host publication | Multicore and Many-core Programming Approaches |
| Publisher | Elsevier Inc. |
| Pages | 229-242 |
| Number of pages | 14 |
| Volume | 2 |
| ISBN (Electronic) | 9780128038901 |
| ISBN (Print) | 9780128038192 |
| DOIs | |
| State | Published - Jul 23 2015 |
| Externally published | Yes |
Funding
These research efforts have been supported by the National Nuclear Security Administration’s PSAAP II project. This work utilized equipment donations to the University of Utah’s Intel Parallel Computing Center (IPCC) at the SCI Institute. We would also like to thank Aaron Knoll, IPCC Principal Investigator, for his assistance along the way.
Keywords
- 61st core
- Compact affinity
- Control thread
- Intel many integrated core architecture (MIC)
- Main thread
- OpenMP
- PThreads
- Radiation modeling
- Reserved core
- Reverse Monte-Carlo ray tracing
- RMCRT
- Scatter affinity
- Selective affinity
- Thread affinity
- Thread placement
- Uintah computational framework