Exploration of OpenCL 2D Convolution Kernels on Intel FPGA, CPU, and GPU Platforms

There is a need to evaluate the resource usage and optimize the performance of the floating-point 2D convolution kernels on a recent FPGA which features large numbers of hardened floating-point digital signal processing blocks and an increasingly large on-chip memory. In this paper, we presented an OpenCL 2D convolution kernel with configurable parameters for specifying the precision, sizes of filter and block, vectorization width, and compute-unit duplication factor. Then, we instantiated a set of specific instances of the kernel with a fixed filter size to evaluate their resource usage and performance to narrow down the exploration space. Based on the evaluation results on an Intelo Arria 10 FPGA using high-level synthesis, we evaluated the kernels with different filter sizes within the pruned exploration space. Compared to the baseline implementation in which the vectorization width is two and the block size is 32times 32, our optimizations improve the performance by a factor ranging from 1. 9X to 3X for the single-precision kernels, and from 2. 2X to 3. 37X for the half-precision kernels. Furthermore, we evaluated the performance and power of the kernels on an Intel^® Xeon^® CPU and an Iris^TM Pro integrated GPU. We found that the FPGA could achieve the highest performance for a 9times 9 filter among the CPU, GPU, and FPGA, but the GPU can achieve the highest performance for other filter sizes.