Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs

Zheming Jin; Jeffrey Vetter

doi:10.1145/3458744.3473360

Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs

Zheming Jin, Jeffrey Vetter

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

SYCL is a promising programming model for heterogeneous computing - allowing a single-source code to target devices from multiple vendors. One significant task performed on these accelerators is a primitive operation for integer sum reduction. This paper presents several SYCL implementations of integer sum reduction - using atomic functions, shared local memory, vectorized memory accesses and parameterized workload sizes - to compare the performance and maturity of SYCL against open-source vendor-specific implementations of the same reduction. For a sufficiently large number of integers, tuning the parameters of our SYCL implementations achieves 1.4X speedup over the open-source implementations on an Intel UHD630 integrated GPU. The SYCL reduction is 3% faster than the templated reduction in Thrust, and 0.3% faster than the device reduction in CUB on an Nvidia P100 GPU. The SYCL reduction is 1.9% faster than the templated reduction in Thrust, and 0.4% faster than the device reduction in CUB on an Nvidia V100 GPU.

Original language	English
Title of host publication	50th International Conference on Parallel Processing Workshop, ICPP 2021 - Proceedings
Publisher	Association for Computing Machinery
ISBN (Electronic)	9781450384414
DOIs	https://doi.org/10.1145/3458744.3473360
State	Published - Aug 9 2021
Event	50th International Conference on Parallel Processing Workshop, ICPP 2021 - Virtual, Online, United States Duration: Aug 9 2021 → Aug 12 2021

Publication series

Name	ACM International Conference Proceeding Series

Conference

Conference	50th International Conference on Parallel Processing Workshop, ICPP 2021
Country/Territory	United States
City	Virtual, Online
Period	08/9/21 → 08/12/21

Funding

We appreciate the reviewers for their comments and criticisms. This research used resources of the Experimental Computing Laboratory at Oak Ridge National Laboratory, which is supported by the Office of Science of the U.S. Department of Energy under Contract No. DE-AC05-00OR22725. The research also used resources of the Intel DevCloud.

Keywords

Cuda
Gpgpu
Opencl
Reduction
Sycl

Access to Document

10.1145/3458744.3473360

Cite this

@inproceedings{eade46357373416594453ac366049a4a,

title = "Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs",

abstract = "SYCL is a promising programming model for heterogeneous computing - allowing a single-source code to target devices from multiple vendors. One significant task performed on these accelerators is a primitive operation for integer sum reduction. This paper presents several SYCL implementations of integer sum reduction - using atomic functions, shared local memory, vectorized memory accesses and parameterized workload sizes - to compare the performance and maturity of SYCL against open-source vendor-specific implementations of the same reduction. For a sufficiently large number of integers, tuning the parameters of our SYCL implementations achieves 1.4X speedup over the open-source implementations on an Intel UHD630 integrated GPU. The SYCL reduction is 3% faster than the templated reduction in Thrust, and 0.3% faster than the device reduction in CUB on an Nvidia P100 GPU. The SYCL reduction is 1.9% faster than the templated reduction in Thrust, and 0.4% faster than the device reduction in CUB on an Nvidia V100 GPU.",

keywords = "Cuda, Gpgpu, Opencl, Reduction, Sycl",

author = "Zheming Jin and Jeffrey Vetter",

note = "Publisher Copyright: {\textcopyright} 2021 ACM.; 50th International Conference on Parallel Processing Workshop, ICPP 2021 ; Conference date: 09-08-2021 Through 12-08-2021",

year = "2021",

month = aug,

day = "9",

doi = "10.1145/3458744.3473360",

language = "English",

series = "ACM International Conference Proceeding Series",

publisher = "Association for Computing Machinery",

booktitle = "50th International Conference on Parallel Processing Workshop, ICPP 2021 - Proceedings",

}

Jin, Z & Vetter, J 2021, Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs. in 50th International Conference on Parallel Processing Workshop, ICPP 2021 - Proceedings. ACM International Conference Proceeding Series, Association for Computing Machinery, 50th International Conference on Parallel Processing Workshop, ICPP 2021, Virtual, Online, United States, 08/9/21. https://doi.org/10.1145/3458744.3473360

Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs. / Jin, Zheming; Vetter, Jeffrey.
50th International Conference on Parallel Processing Workshop, ICPP 2021 - Proceedings. Association for Computing Machinery, 2021. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs

AU - Jin, Zheming

AU - Vetter, Jeffrey

PY - 2021/8/9

Y1 - 2021/8/9

N2 - SYCL is a promising programming model for heterogeneous computing - allowing a single-source code to target devices from multiple vendors. One significant task performed on these accelerators is a primitive operation for integer sum reduction. This paper presents several SYCL implementations of integer sum reduction - using atomic functions, shared local memory, vectorized memory accesses and parameterized workload sizes - to compare the performance and maturity of SYCL against open-source vendor-specific implementations of the same reduction. For a sufficiently large number of integers, tuning the parameters of our SYCL implementations achieves 1.4X speedup over the open-source implementations on an Intel UHD630 integrated GPU. The SYCL reduction is 3% faster than the templated reduction in Thrust, and 0.3% faster than the device reduction in CUB on an Nvidia P100 GPU. The SYCL reduction is 1.9% faster than the templated reduction in Thrust, and 0.4% faster than the device reduction in CUB on an Nvidia V100 GPU.

AB - SYCL is a promising programming model for heterogeneous computing - allowing a single-source code to target devices from multiple vendors. One significant task performed on these accelerators is a primitive operation for integer sum reduction. This paper presents several SYCL implementations of integer sum reduction - using atomic functions, shared local memory, vectorized memory accesses and parameterized workload sizes - to compare the performance and maturity of SYCL against open-source vendor-specific implementations of the same reduction. For a sufficiently large number of integers, tuning the parameters of our SYCL implementations achieves 1.4X speedup over the open-source implementations on an Intel UHD630 integrated GPU. The SYCL reduction is 3% faster than the templated reduction in Thrust, and 0.3% faster than the device reduction in CUB on an Nvidia P100 GPU. The SYCL reduction is 1.9% faster than the templated reduction in Thrust, and 0.4% faster than the device reduction in CUB on an Nvidia V100 GPU.

KW - Cuda

KW - Gpgpu

KW - Opencl

KW - Reduction

KW - Sycl

UR - http://www.scopus.com/inward/record.url?scp=85115986629&partnerID=8YFLogxK

U2 - 10.1145/3458744.3473360

DO - 10.1145/3458744.3473360

M3 - Conference contribution

AN - SCOPUS:85115986629

T3 - ACM International Conference Proceeding Series

BT - 50th International Conference on Parallel Processing Workshop, ICPP 2021 - Proceedings

PB - Association for Computing Machinery

T2 - 50th International Conference on Parallel Processing Workshop, ICPP 2021

Y2 - 9 August 2021 through 12 August 2021

ER -

Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs

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