TY - GEN
T1 - Evaluating Nonuniform Reduction in HIP and SYCL on GPUs
AU - Jin, Zheming
AU - Vetter, Jeffrey S.
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Motivated by maturing programming models and portability for heterogeneous computing, we describe the challenges posed by hardware architectures and programming models when migrating an optimized implementation of nonuniform reduction from CUDA to HIP and SYCL. We explain the migration experience, evaluate the performance of the reduction on GPU -based computing platforms, and provide feedback on improving portability for the development of the SYCL programming model.
AB - Motivated by maturing programming models and portability for heterogeneous computing, we describe the challenges posed by hardware architectures and programming models when migrating an optimized implementation of nonuniform reduction from CUDA to HIP and SYCL. We explain the migration experience, evaluate the performance of the reduction on GPU -based computing platforms, and provide feedback on improving portability for the development of the SYCL programming model.
KW - Nonuniform reduction
KW - heterogeneous computing
KW - programming model
UR - http://www.scopus.com/inward/record.url?scp=85147798660&partnerID=8YFLogxK
U2 - 10.1109/DRBSD56682.2022.00010
DO - 10.1109/DRBSD56682.2022.00010
M3 - Conference contribution
AN - SCOPUS:85147798660
T3 - Proceedings of DRBSD-8 2022: 8th International Workshop on Data Analysis and Reduction for Big Scientific Data, Held in conjunction with SC 2022: The International Conference for High Performance Computing, Networking, Storage and Analysis
SP - 37
EP - 43
BT - Proceedings of DRBSD-8 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th IEEE/ACM International Workshop on Data Analysis and Reduction for Big Scientific Data, DRBSD-8 2022
Y2 - 13 November 2022 through 18 November 2022
ER -