Abstract
Field-programmable gate array (FPGA) is a promising choice as a heterogeneous computing component for energy-aware applications in high-performance computing. Emerging high-level synthesis tools such as Intel OpenCL SDK offer a streamlined design flow to facilitate the use of FPGAs for scientists and researchers. Focused on the HACCmk kernel routine as a case study, we explore the kernel optimization space and their performance implications. We describe the resource usage, performance, and performance per watt of the kernel implementations in OpenCL. Using directives for accelerator programming, the performance per watt on an Intel Arria10-based FPGA platform can achieve 2.5X improvement over that on an Intel Xeon 16-core CPU, and 2.1X improvement over that on an Nvidia K80 GPU, while trading off 50% of performance.
Original language | English |
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Title of host publication | 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781538659892 |
DOIs | |
State | Published - Nov 26 2018 |
Externally published | Yes |
Event | 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018 - Waltham, United States Duration: Sep 25 2018 → Sep 27 2018 |
Publication series
Name | 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018 |
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Conference
Conference | 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018 |
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Country/Territory | United States |
City | Waltham |
Period | 09/25/18 → 09/27/18 |
Funding
We are sincerely grateful to the reviewers for their constructive comments. The research work was supported by the U.S. Department of Energy, Office of Science, under contract DE-AC02-06CH11357.
Keywords
- FPGA
- HACCmk
- High-level Synthesis