Evaluating an OpenCL FPGA Platform for HPC: A Case Study with the HACCmk Kernel

Zheming Jin, Hal Finkel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Field-programmable gate array (FPGA) is a promising choice as a heterogeneous computing component for energy-aware applications in high-performance computing. Emerging high-level synthesis tools such as Intel OpenCL SDK offer a streamlined design flow to facilitate the use of FPGAs for scientists and researchers. Focused on the HACCmk kernel routine as a case study, we explore the kernel optimization space and their performance implications. We describe the resource usage, performance, and performance per watt of the kernel implementations in OpenCL. Using directives for accelerator programming, the performance per watt on an Intel Arria10-based FPGA platform can achieve 2.5X improvement over that on an Intel Xeon 16-core CPU, and 2.1X improvement over that on an Nvidia K80 GPU, while trading off 50% of performance.

Original languageEnglish
Title of host publication2018 IEEE High Performance Extreme Computing Conference, HPEC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538659892
DOIs
StatePublished - Nov 26 2018
Externally publishedYes
Event2018 IEEE High Performance Extreme Computing Conference, HPEC 2018 - Waltham, United States
Duration: Sep 25 2018Sep 27 2018

Publication series

Name2018 IEEE High Performance Extreme Computing Conference, HPEC 2018

Conference

Conference2018 IEEE High Performance Extreme Computing Conference, HPEC 2018
Country/TerritoryUnited States
CityWaltham
Period09/25/1809/27/18

Funding

We are sincerely grateful to the reviewers for their constructive comments. The research work was supported by the U.S. Department of Energy, Office of Science, under contract DE-AC02-06CH11357.

Keywords

  • FPGA
  • HACCmk
  • High-level Synthesis

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