TY - GEN
T1 - Estimation and minimization of power loop inductance in 135 kW SiC traction inverter
AU - Aberg, Bryce
AU - Moorthy, Radha Sree Krishna
AU - Yang, Li
AU - Yu, Wensong
AU - Husain, Iqbal
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/18
Y1 - 2018/4/18
N2 - The paper discusses the estimation and minimization of commutation loop inductance for a printed circuit board (PCB) busbar based 135 kW SiC inverter with a 1 kV DC link using finite element analysis (FEA) simulations. For the inductance estimation of the power module (Wolfspeed: HT-3231-R), PCB busbar, and customized interconnects constituting the commutation loop have been modelled accurately in Ansys Q3D Extractor. Based on the simulation results, subsequent modification to the original PCB busbar design has been proposed to lower the loop inductance. FEA simulation results have resulted in an optimized PCB busbar with lower commutation loop inductance, thereby limiting the device voltage spike well below its rated value. Loop inductance results from the Q3D simulation have been validated through double pulse tests (DPT) and the performance improvements achieved therefore have been highlighted.
AB - The paper discusses the estimation and minimization of commutation loop inductance for a printed circuit board (PCB) busbar based 135 kW SiC inverter with a 1 kV DC link using finite element analysis (FEA) simulations. For the inductance estimation of the power module (Wolfspeed: HT-3231-R), PCB busbar, and customized interconnects constituting the commutation loop have been modelled accurately in Ansys Q3D Extractor. Based on the simulation results, subsequent modification to the original PCB busbar design has been proposed to lower the loop inductance. FEA simulation results have resulted in an optimized PCB busbar with lower commutation loop inductance, thereby limiting the device voltage spike well below its rated value. Loop inductance results from the Q3D simulation have been validated through double pulse tests (DPT) and the performance improvements achieved therefore have been highlighted.
KW - Busbar design
KW - Commutation loop inductance
KW - FEA simulations
KW - PCB busbar
KW - Parasitic inductances
KW - SiC inverter
UR - http://www.scopus.com/inward/record.url?scp=85046958928&partnerID=8YFLogxK
U2 - 10.1109/APEC.2018.8341257
DO - 10.1109/APEC.2018.8341257
M3 - Conference contribution
AN - SCOPUS:85046958928
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1772
EP - 1777
BT - APEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
Y2 - 4 March 2018 through 8 March 2018
ER -