EqualChance: Addressing intra-set write variation to increase lifetime of non-volatile caches

Sparsh Mittal; Jeffrey S. Vetter

EqualChance: Addressing intra-set write variation to increase lifetime of non-volatile caches

Research output: Contribution to conference › Paper › peer-review

23 Scopus citations

Abstract

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of nonvolatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29×. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

Original language	English
State	Published - 2014
Externally published	Yes
Event	2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, INFLOW 2014 - Broomfield, United States Duration: Oct 5 2014 → …

Conference

Conference	2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, INFLOW 2014
Country/Territory	United States
City	Broomfield
Period	10/5/14 → …

Funding

Support for this work was provided by U.S. Department of Energy, Office of Science, Advanced Scientific Computing Research. The work was performed at the Oak Ridge National Laboratory, which is managed by UT-Battelle, LLC under Contract No. DE-AC05-00OR22725 to the U.S. Government. Accordingly, the U.S. Government retains a non-exclusive, royalty-free license to publish or reproduce the published form of this contribution, or allow others to do so, for U.S. Government purposes. This research is sponsored by the Office of Advanced Scientific Computing Research in the U.S. Department of Energy.

Keywords

Cache lifetime
Intra-set write variation
Non-volatile memory
ReRAM
Wear-leveling
Write endurance

Cite this

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title = "EqualChance: Addressing intra-set write variation to increase lifetime of non-volatile caches",

abstract = "To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of nonvolatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29×. Also, its implementation overhead is small, and it incurs very small performance and energy loss.",

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T1 - EqualChance

T2 - 2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, INFLOW 2014

AU - Mittal, Sparsh

AU - Vetter, Jeffrey S.

PY - 2014

Y1 - 2014

N2 - To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of nonvolatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29×. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

AB - To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of nonvolatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29×. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

KW - Cache lifetime

KW - Intra-set write variation

KW - Non-volatile memory

KW - ReRAM

KW - Wear-leveling

KW - Write endurance

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M3 - Paper

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Y2 - 5 October 2014

ER -

EqualChance: Addressing intra-set write variation to increase lifetime of non-volatile caches

Abstract

Conference

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Keywords

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