TY - JOUR
T1 - Energy efficient decoder design for nonbinary LDPC codes
AU - Yasodha, T.
AU - Jocobraglend, I.
AU - Meena Alias Jeyanthi, K.
N1 - Publisher Copyright:
© Springer India 2015.
PY - 2015
Y1 - 2015
N2 - Increased SNR and Reduced BER is being the aim of wireless CDMA systems. Coding plays a major role in achieving the target. LDPC codes are being the desired ones in achieving reduced area and power input. This paper presents a high performance error detection and correction for non-binary low density parity check codes (LDPC). Check node processing is formulated by using Euclidean graph decoding architecture. The proposed decoding method reduces the number of iterations and achieves reduction in area and power. EG-Decoder with Q-ary sum product algorithm is implemented in log domain and reduced power of 0.6080 mW and area of 2.17 MB is achieved.
AB - Increased SNR and Reduced BER is being the aim of wireless CDMA systems. Coding plays a major role in achieving the target. LDPC codes are being the desired ones in achieving reduced area and power input. This paper presents a high performance error detection and correction for non-binary low density parity check codes (LDPC). Check node processing is formulated by using Euclidean graph decoding architecture. The proposed decoding method reduces the number of iterations and achieves reduction in area and power. EG-Decoder with Q-ary sum product algorithm is implemented in log domain and reduced power of 0.6080 mW and area of 2.17 MB is achieved.
KW - Euclidean graph
KW - Non-binary LDPC codes
KW - Q-ary sum product algorithm
UR - http://www.scopus.com/inward/record.url?scp=84911874570&partnerID=8YFLogxK
U2 - 10.1007/978-81-322-2119-7_146
DO - 10.1007/978-81-322-2119-7_146
M3 - Article
AN - SCOPUS:84911874570
SN - 1876-1100
VL - 326
SP - 1497
EP - 1507
JO - Lecture Notes in Electrical Engineering
JF - Lecture Notes in Electrical Engineering
ER -
