Enabling power density and thermal-aware floorplanning

With temperature being one of the main limiting factors in design of high performance processors, early evaluation of thermal effects in design stages is becoming a necessity. Floorplanning is an imperative step in the design process where thermal effects can be taken into account. This work studies a thermal-aware floorplanning scheme, with the goal of increasing both reliability and performance measures of the design. We show that a majority of thermal emergencies can be averted by a) leveraging the lateral heat transfer effects (as has been shown previously), and b) by reducing the power density of thermally critical blocks. The former becomes possible through moving, and modifying the aspect-ratio of the blocks in the floorplanning process. The latter, one of the key contributions of this work, is carried out through resizing of functional blocks in a controlled way. We also propose a selective power map generation method for the floorplanning process. In this method the time windows in which thermal emergencies occur guide the power map generation. As a result, we observed an 8.8% performance improvement, and a 40% reliability increase with the area overhead of just 3%.