Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors

Robin Khosla; Deepak K. Sharma; Kunal Mondal; Satinder K. Sharma

doi:10.1063/1.4897952

Effect of electrical stress on Au/Pb (Zr_0.52Ti_0.48) O₃/TiO_xN_y/Si gate stack for reliability analysis of ferroelectric field effect transistors

Robin Khosla, Deepak K. Sharma, Kunal Mondal, Satinder K. Sharma

Research output: Contribution to journal › Article › peer-review

17 Scopus citations

Abstract

Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiO_xN_y) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm² under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiO_xN_y buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (C_H) and low (C_L) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiO_xN_y, respectively. Thus, Au/PZT/TiO_xN_y/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.

Original language	English
Article number	152907
Journal	Applied Physics Letters
Volume	105
Issue number	15
DOIs	https://doi.org/10.1063/1.4897952
State	Published - Oct 13 2014
Externally published	Yes

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@article{910c28340d85412b8c2644f426fc3745,

title = "Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors",

abstract = "Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, respectively. Thus, Au/PZT/TiOxNy/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.",

author = "Robin Khosla and Sharma, {Deepak K.} and Kunal Mondal and Sharma, {Satinder K.}",

note = "Publisher Copyright: {\textcopyright} 2014 AIP Publishing LLC.",

year = "2014",

month = oct,

day = "13",

doi = "10.1063/1.4897952",

language = "English",

volume = "105",

journal = "Applied Physics Letters",

issn = "0003-6951",

publisher = "American Institute of Physics",

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AU - Khosla, Robin

AU - Sharma, Deepak K.

AU - Mondal, Kunal

AU - Sharma, Satinder K.

PY - 2014/10/13

Y1 - 2014/10/13

N2 - Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, respectively. Thus, Au/PZT/TiOxNy/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.

AB - Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, respectively. Thus, Au/PZT/TiOxNy/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.

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Effect of electrical stress on Au/Pb (Zr_0.52Ti_0.48) O₃/TiO_xN_y/Si gate stack for reliability analysis of ferroelectric field effect transistors

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