Development of a front end controller/heap manager for PHENIX

M. N. Ericson; M. D. Allen; M. S. Musrock; J. W. Walker; C. L. Britton; A. L. Wintenberg; G. R. Young

Development of a front end controller/heap manager for PHENIX

M. N. Ericson, M. D. Allen, M. S. Musrock, J. W. Walker, C. L. Britton, A. L. Wintenberg, G. R. Young

Sensors and Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

Original language	English
Pages	60-64
Number of pages	5
State	Published - 1996
Event	Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) - Anaheim, CA, USA Duration: Nov 2 1996 → Nov 9 1996

Conference

Conference	Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)
City	Anaheim, CA, USA
Period	11/2/96 → 11/9/96

Cite this

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title = "Development of a front end controller/heap manager for PHENIX",

abstract = "A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.",

author = "Ericson, {M. N.} and Allen, {M. D.} and Musrock, {M. S.} and Walker, {J. W.} and Britton, {C. L.} and Wintenberg, {A. L.} and Young, {G. R.}",

year = "1996",

language = "English",

pages = "60--64",

note = "Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) ; Conference date: 02-11-1996 Through 09-11-1996",

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T1 - Development of a front end controller/heap manager for PHENIX

AU - Ericson, M. N.

AU - Allen, M. D.

AU - Musrock, M. S.

AU - Walker, J. W.

AU - Britton, C. L.

AU - Wintenberg, A. L.

AU - Young, G. R.

PY - 1996

Y1 - 1996

N2 - A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

AB - A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

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T2 - Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)

Y2 - 2 November 1996 through 9 November 1996

ER -

Development of a front end controller/heap manager for PHENIX

Abstract

Conference

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