@inproceedings{880aca9c3107415eb02422cc66a18458,
title = "DESTINY: A tool for modeling emerging 3D NVM and eDRAM caches",
abstract = "The continuous drive for performance has pushed the researchers to explore novel memory technologies (e.g. nonvolatile memory) and novel fabrication approaches (e.g. 3D stacking) in the design of caches. However, a comprehensive tool which models both conventional and emerging memory technologies for both 2D and 3D designs has been lacking. We present DESTINY, a microarchitecture-level tool for modeling 3D (and 2D) cache designs using SRAM, embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM) and phase change RAM (PCM). DESTINY facilitates design-space exploration across several dimensions, such as optimizing for a target (e.g. latency or area) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a desired optimization target etc. DESTINY has been validated against industrial cache prototypes. We believe that DESTINY will drive architecture and system-level studies and will be useful for researchers and designers.",
keywords = "Cache, PCM, ReRAM, SRAM, STT-RAM, eDRAM, modeling tool, non-volatile memory (NVM or NVRAM), validation",
author = "Matt Poremba and Sparsh Mittal and Dong Li and Vetter, {Jeffrey S.} and Yuan Xie",
note = "Publisher Copyright: {\textcopyright} 2015 EDAA.; 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 ; Conference date: 09-03-2015 Through 13-03-2015",
year = "2015",
month = apr,
day = "22",
doi = "10.7873/date.2015.0733",
language = "English",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1543--1546",
booktitle = "Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015",
}