TY - JOUR
T1 - Designing a hamming coder/decoder using QCAs
AU - Ziabari, Mirmansour
AU - Kassai, Ahmad Mohades
AU - Ziabari, Amirkoushyar
AU - Maklavani, Shahin Enayati
PY - 2008
Y1 - 2008
N2 - In this research, the arithmetic structures of Hamming coder/decoder are discussed and a general formula for the case of a single bit error in composite dataword parity bits is derived and using this formula a design work for logic circuitry which functions as Hamming coder/decoder and exclusively is composed of XOR-gates is presented. The advantages of unique capabilities of Quantum dot Cellular Automata (QCA) are stated. Then many design consideration are described and showed that how NAND/NOR operations routing mechanism can be implemented using QCAs. Substituting these blocks with XORs leads to a design work which is completely composed of NAND gates and in turn of QCAs. For the reason of complexity of the final design work, the advantage of an advanced software tool i.e., the QCADesigner for final implementation of the QCA network is taken. To minimize total delay and chip area and in turn total manufacturing cost the design work is so modified that the number of clocking zone between input and output to be minimum and this can be the reason of superiority of the proposed design work.
AB - In this research, the arithmetic structures of Hamming coder/decoder are discussed and a general formula for the case of a single bit error in composite dataword parity bits is derived and using this formula a design work for logic circuitry which functions as Hamming coder/decoder and exclusively is composed of XOR-gates is presented. The advantages of unique capabilities of Quantum dot Cellular Automata (QCA) are stated. Then many design consideration are described and showed that how NAND/NOR operations routing mechanism can be implemented using QCAs. Substituting these blocks with XORs leads to a design work which is completely composed of NAND gates and in turn of QCAs. For the reason of complexity of the final design work, the advantage of an advanced software tool i.e., the QCADesigner for final implementation of the QCA network is taken. To minimize total delay and chip area and in turn total manufacturing cost the design work is so modified that the number of clocking zone between input and output to be minimum and this can be the reason of superiority of the proposed design work.
KW - Clocking zone
KW - QCA chip
KW - QCA routing element
KW - Single bit error
UR - http://www.scopus.com/inward/record.url?scp=67649229761&partnerID=8YFLogxK
U2 - 10.3923/jas.2008.2569.2576
DO - 10.3923/jas.2008.2569.2576
M3 - Article
AN - SCOPUS:67649229761
SN - 1812-5654
VL - 8
SP - 2569
EP - 2576
JO - Journal of Applied Sciences
JF - Journal of Applied Sciences
IS - 14
ER -