Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

Lloyd G. Clonts; Donald W. Bouldin

doi:10.1109/ASIC.1992.270203

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A new architecture has been developed to reduce the instruction-time execution of a microprocessor compatible with the Intel 80C51. This higher performance is achieved by executing all instructions in a minimum number of clock cycles. Dual edge-triggered flip-flops, selective clocking of components, and a hardware-oriented structure are incorporated to produce a processor which has better throughput and lower power dissipation than the Intel 80C51. The new architecture focuses on combining increased performance with low power dissipation.

Original language	English
Title of host publication	Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
Publisher	IEEE Computer Society
Pages	545-548
Number of pages	4
ISBN (Electronic)	0780307682
DOIs	https://doi.org/10.1109/ASIC.1992.270203
State	Published - 1992
Externally published	Yes
Event	5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States Duration: Sep 21 1992 → Sep 25 1992

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
Country/Territory	United States
City	Rochester
Period	09/21/92 → 09/25/92

Funding

This research was sponsored by the U.S.Navy RADIAC Development Program under DOE Interagency Agreement No. 1868B135-Al. The work was performed under contract with the University of Tennessee, Knoxville at the Oak Ridge National Laboratory. The authors wish to thank W.L. Bryan and D.F. Newport for their contributions to this work.

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10.1109/ASIC.1992.270203

Cite this

Clonts, L. G., & Bouldin, D. W. (1992). Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution. In Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 (pp. 545-548). Article 270203 (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASIC.1992.270203

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title = "Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution",

abstract = "A new architecture has been developed to reduce the instruction-time execution of a microprocessor compatible with the Intel 80C51. This higher performance is achieved by executing all instructions in a minimum number of clock cycles. Dual edge-triggered flip-flops, selective clocking of components, and a hardware-oriented structure are incorporated to produce a processor which has better throughput and lower power dissipation than the Intel 80C51. The new architecture focuses on combining increased performance with low power dissipation.",

author = "Clonts, {Lloyd G.} and Bouldin, {Donald W.}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 ; Conference date: 21-09-1992 Through 25-09-1992",

year = "1992",

doi = "10.1109/ASIC.1992.270203",

language = "English",

series = "Proceedings of International Conference on ASIC",

publisher = "IEEE Computer Society",

pages = "545--548",

booktitle = "Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992",

}

Clonts, LG & Bouldin, DW 1992, Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution. in Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992., 270203, Proceedings of International Conference on ASIC, IEEE Computer Society, pp. 545-548, 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992, Rochester, United States, 09/21/92. https://doi.org/10.1109/ASIC.1992.270203

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution. / Clonts, Lloyd G.; Bouldin, Donald W.
Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992. IEEE Computer Society, 1992. p. 545-548 270203 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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BT - Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992

PB - IEEE Computer Society

T2 - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992

Y2 - 21 September 1992 through 25 September 1992

ER -

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

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