Design and performance of beam test electronics for the PHENIX multiplicity vertex detector

C. L. Britton; W. L. Bryan; M. S. Emery; M. N. Ericson; M. S. Musrock; M. L. Simpson; M. C. Smith; J. W. Walker; A. L. Wintenberg; G. R. Young; M. D. Allen; L. G. Clonts; R. L. Jones; E. J. Kennedy; R. S. Smith

Design and performance of beam test electronics for the PHENIX multiplicity vertex detector

C. L. Britton, W. L. Bryan, M. S. Emery, M. N. Ericson, M. S. Musrock, M. L. Simpson, M. C. Smith, J. W. Walker, A. L. Wintenberg, G. R. Young, M. D. Allen, L. G. Clonts, R. L. Jones, E. J. Kennedy, R. S. Smith

Sensors and Electronics

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μ n-well CMOS process used for preamplifier fabrication.

Original language	English
Pages	6-10
Number of pages	5
State	Published - 1996
Event	Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) - Anaheim, CA, USA Duration: Nov 2 1996 → Nov 9 1996

Conference

Conference	Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)
City	Anaheim, CA, USA
Period	11/2/96 → 11/9/96

Cite this

Britton, C. L., Bryan, W. L., Emery, M. S., Ericson, M. N., Musrock, M. S., Simpson, M. L., Smith, M. C., Walker, J. W., Wintenberg, A. L., Young, G. R., Allen, M. D., Clonts, L. G., Jones, R. L., Kennedy, E. J., & Smith, R. S. (1996). Design and performance of beam test electronics for the PHENIX multiplicity vertex detector. 6-10. Paper presented at Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3), Anaheim, CA, USA.

@conference{ae98c254d9784e399e31940737e23d6b,

title = "Design and performance of beam test electronics for the PHENIX multiplicity vertex detector",

abstract = "The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μ n-well CMOS process used for preamplifier fabrication.",

author = "Britton, {C. L.} and Bryan, {W. L.} and Emery, {M. S.} and Ericson, {M. N.} and Musrock, {M. S.} and Simpson, {M. L.} and Smith, {M. C.} and Walker, {J. W.} and Wintenberg, {A. L.} and Young, {G. R.} and Allen, {M. D.} and Clonts, {L. G.} and Jones, {R. L.} and Kennedy, {E. J.} and Smith, {R. S.}",

year = "1996",

language = "English",

pages = "6--10",

note = "Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) ; Conference date: 02-11-1996 Through 09-11-1996",

}

Britton, CL, Bryan, WL, Emery, MS, Ericson, MN, Musrock, MS, Simpson, ML, Smith, MC, Walker, JW, Wintenberg, AL, Young, GR, Allen, MD, Clonts, LG, Jones, RL, Kennedy, EJ & Smith, RS 1996, 'Design and performance of beam test electronics for the PHENIX multiplicity vertex detector', Paper presented at Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3), Anaheim, CA, USA, 11/2/96 - 11/9/96 pp. 6-10.

TY - CONF

T1 - Design and performance of beam test electronics for the PHENIX multiplicity vertex detector

AU - Britton, C. L.

AU - Bryan, W. L.

AU - Emery, M. S.

AU - Ericson, M. N.

AU - Musrock, M. S.

AU - Simpson, M. L.

AU - Smith, M. C.

AU - Walker, J. W.

AU - Wintenberg, A. L.

AU - Young, G. R.

AU - Allen, M. D.

AU - Clonts, L. G.

AU - Jones, R. L.

AU - Kennedy, E. J.

AU - Smith, R. S.

PY - 1996

Y1 - 1996

N2 - The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μ n-well CMOS process used for preamplifier fabrication.

AB - The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μ n-well CMOS process used for preamplifier fabrication.

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M3 - Paper

AN - SCOPUS:0030374320

SP - 6

EP - 10

T2 - Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)

Y2 - 2 November 1996 through 9 November 1996

ER -

Design and performance of beam test electronics for the PHENIX multiplicity vertex detector

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