Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

C. L. Britton; W. L. Bryan; M. S. Emery; M. N. Ericson; M. S. Musrock; M. L. Simpson; M. C. Smith; J. W. Walker; A. L. Wintenberg; G. R. Young; M. D. Allen; L. G. Clonts; R. L. Jones; E. J. Kennedy; R. S. Smith; J. Boissevain; B. V. Jacak; D. Jaffe; J. S. Kapustinsky; J. Simon-Gillo; J. P. Sullivan; H. Van Hecke; N. Xu

doi:10.1109/23.603657

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

C. L. Britton, W. L. Bryan, M. S. Emery, M. N. Ericson, M. S. Musrock, M. L. Simpson, M. C. Smith, J. W. Walker, A. L. Wintenberg, G. R. Young, M. D. Allen, L. G. Clonts, R. L. Jones, E. J. Kennedy, R. S. Smith, J. Boissevain, B. V. Jacak, D. Jaffe, J. S. Kapustinsky, J. Simon-GilloJ. P. Sullivan, H. Van Hecke, N. Xu

Sensors and Electronics

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Abstract

The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μm n-well CMOS process used for preamplifier fabrication.

Original language	English
Pages (from-to)	283-288
Number of pages	6
Journal	IEEE Transactions on Nuclear Science
Volume	44
Issue number	3 PART 1
DOIs	https://doi.org/10.1109/23.603657
State	Published - 1997

Funding

The MVD is a 2-layer barrel detector comprised of 112 strip detectors and 2 disk-shaped end caps comprised of 24 wedge-shaped pad detectors. It is a clam-shell design, constructed in two halves to close about the beam pipe. The main physics goals of the detector are to provide a multiplicity 'Research sponsored by the U.S. Department of Energy and performed at Oak Ridge National Laboratory, managed by Lockheed Martin Energy Research Corporation for the U.S. Department of Energy under Contract No. DE-AC05-960R22464.

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Britton, C. L., Bryan, W. L., Emery, M. S., Ericson, M. N., Musrock, M. S., Simpson, M. L., Smith, M. C., Walker, J. W., Wintenberg, A. L., Young, G. R., Allen, M. D., Clonts, L. G., Jones, R. L., Kennedy, E. J., Smith, R. S., Boissevain, J., Jacak, B. V., Jaffe, D., Kapustinsky, J. S., ... Xu, N. (1997). Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector. IEEE Transactions on Nuclear Science, 44(3 PART 1), 283-288. https://doi.org/10.1109/23.603657

@article{2fca3f0dcccd43f782e52254b321aee9,

title = "Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector",

abstract = "The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μm n-well CMOS process used for preamplifier fabrication.",

author = "Britton, {C. L.} and Bryan, {W. L.} and Emery, {M. S.} and Ericson, {M. N.} and Musrock, {M. S.} and Simpson, {M. L.} and Smith, {M. C.} and Walker, {J. W.} and Wintenberg, {A. L.} and Young, {G. R.} and Allen, {M. D.} and Clonts, {L. G.} and Jones, {R. L.} and Kennedy, {E. J.} and Smith, {R. S.} and J. Boissevain and Jacak, {B. V.} and D. Jaffe and Kapustinsky, {J. S.} and J. Simon-Gillo and Sullivan, {J. P.} and {Van Hecke}, H. and N. Xu",

year = "1997",

doi = "10.1109/23.603657",

language = "English",

volume = "44",

pages = "283--288",

journal = "IEEE Transactions on Nuclear Science",

issn = "0018-9499",

publisher = "Institute of Electrical and Electronics Engineers",

number = "3 PART 1",

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Britton, CL, Bryan, WL, Emery, MS, Ericson, MN, Musrock, MS, Simpson, ML, Smith, MC, Walker, JW, Wintenberg, AL, Young, GR, Allen, MD, Clonts, LG, Jones, RL, Kennedy, EJ, Smith, RS, Boissevain, J, Jacak, BV, Jaffe, D, Kapustinsky, JS, Simon-Gillo, J, Sullivan, JP, Van Hecke, H & Xu, N 1997, 'Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector', IEEE Transactions on Nuclear Science, vol. 44, no. 3 PART 1, pp. 283-288. https://doi.org/10.1109/23.603657

TY - JOUR

T1 - Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

AU - Britton, C. L.

AU - Bryan, W. L.

AU - Emery, M. S.

AU - Ericson, M. N.

AU - Musrock, M. S.

AU - Simpson, M. L.

AU - Smith, M. C.

AU - Walker, J. W.

AU - Wintenberg, A. L.

AU - Young, G. R.

AU - Allen, M. D.

AU - Clonts, L. G.

AU - Jones, R. L.

AU - Kennedy, E. J.

AU - Smith, R. S.

AU - Boissevain, J.

AU - Jacak, B. V.

AU - Jaffe, D.

AU - Kapustinsky, J. S.

AU - Simon-Gillo, J.

AU - Sullivan, J. P.

AU - Van Hecke, H.

AU - Xu, N.

PY - 1997

Y1 - 1997

N2 - The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μm n-well CMOS process used for preamplifier fabrication.

AB - The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μm n-well CMOS process used for preamplifier fabrication.

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DO - 10.1109/23.603657

M3 - Article

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SN - 0018-9499

VL - 44

SP - 283

EP - 288

JO - IEEE Transactions on Nuclear Science

JF - IEEE Transactions on Nuclear Science

IS - 3 PART 1

ER -

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

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