TY - GEN
T1 - Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File
AU - Mittal, Sparsh
AU - Wang, Haonan
AU - Jog, Adwait
AU - Vetter, Jeffrey S.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/3/21
Y1 - 2017/3/21
N2 - Modern graphics processing units (GPUs) are using increasingly larger register file (RF) which occupies a large fraction of GPU core area and is very frequently accessed. This makes RF vulnerable to soft-errors (SE). In this paper, we present two techniques for improving SE resilience of GPU RF. First, we propose compressing the RF values for reducing the number of vulnerable bits. We leverage value similarity and the presence of narrow-width values to perform compression at warp or thread-level, respectively. Second, we propose selective hardening to design a portion of register entry with SE immune circuits. By collectively using these techniques, higher resilience can be provided with lower overhead. Without hardening, our warp and thread-level compression techniques bring 47.0% and 40.8% reduction in SE vulnerability, respectively.
AB - Modern graphics processing units (GPUs) are using increasingly larger register file (RF) which occupies a large fraction of GPU core area and is very frequently accessed. This makes RF vulnerable to soft-errors (SE). In this paper, we present two techniques for improving SE resilience of GPU RF. First, we propose compressing the RF values for reducing the number of vulnerable bits. We leverage value similarity and the presence of narrow-width values to perform compression at warp or thread-level, respectively. Second, we propose selective hardening to design a portion of register entry with SE immune circuits. By collectively using these techniques, higher resilience can be provided with lower overhead. Without hardening, our warp and thread-level compression techniques bring 47.0% and 40.8% reduction in SE vulnerability, respectively.
KW - GPU
KW - data compression
KW - narrow-value detection
KW - register file
KW - soft-error resilience
UR - http://www.scopus.com/inward/record.url?scp=85018336178&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2017.14
DO - 10.1109/VLSID.2017.14
M3 - Conference contribution
AN - SCOPUS:85018336178
T3 - Proceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017
SP - 409
EP - 414
BT - Proceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017
Y2 - 7 January 2017 through 11 January 2017
ER -