Abstract
The high capital expenditure (capex) necessary to manufacture crystalline silicon PV modules negatively affects the levelized cost of electricity (¢/kWh) and critically impacts the rate at which the PV industry can scale up. Wafer, cell, and module fabrication with thin free-standing silicon wafers is one key to reduce capex. Thin wafers reduce capex associated with silicon refining and wafer fabrication, which together sum to 58% of the total capex of silicon module manufacturing. In addition, thin wafers directly and significantly reduce variable costs. However, introducing 50 μm thin free-standing wafers into today's manufacturing lines result in cracking, creating a yield-based disincentive. Due to the brittle nature of silicon, wafer breakage is the major concern due to the high stress that is induced during processes in manufacturing lines. In this paper, we describe an improved method for edge micro-crack detection that can help enable low-capex, thin free-standing Si wafers. We present a method of detecting and measuring cracks along wafer edges by using a dark-field IR scattering imaging technique which enables detection of edge cracks at the micron scale.
| Original language | English |
|---|---|
| Pages (from-to) | 526-531 |
| Number of pages | 6 |
| Journal | Energy Procedia |
| Volume | 124 |
| DOIs | |
| State | Published - 2017 |
| Externally published | Yes |
| Event | 7th International Conference on Silicon Photovoltaics, SiliconPV 2017 - Freiburg, Germany Duration: Apr 3 2017 → Apr 5 2017 |
Funding
This work was supported by the DE O under award no. DE-EE0007535. This work was performed in part at the Harvard University Center for Nanoscale Systems (CNS), a member of the National aN notechnology Coordinated Infrastructure Network (CNN I), which is supported by the National Science Foundation under SN F EECS award no. 1541959.
Keywords
- Capex
- IR scattering
- dark-field imaging
- edge crack detection
- polysilicon
- thin free-standing wafer