TY - GEN
T1 - Cooling power optimization for hybrid solid-state and liquid cooling in integrated circuit chips with hotspots
AU - Yazawa, Kazuaki
AU - Ziabari, Amirkoushyar
AU - Koh, Yee Rui
AU - Shakouri, Ali
AU - Sahu, Vivek
AU - Fedorov, Andrei G.
AU - Joshi, Yogendra
PY - 2012
Y1 - 2012
N2 - We report theoretical investigation and optimization of a hot-spot cooling method. This hybrid scheme contains a liquid cooling microchannel and superlattice hotspot cooler(s). This analysis of the hybrid method aims to solve the potential thermal management challenges for hotspots especially in 3D stacked multichip packaging. The goal is to reduce the overall cooling power and optimize the energy efficiency. Starting with a generic modeling of the superlattice cooler system, the cooling temperature as a function of the superlattice thickness and the driving current is found. The analytic results are then compared with full 3D numerical simulation. The role of spreading thermal resistance in the chip substrate was found to be important. The later part of this report is the integration of the microchannel with the hotspot cooler. The pumping power is modeled based on the microchannel design and fluid properties. The total cooling power, the sum of the electrical power to pump the liquid and the electrical power to drive the superlattice cooler, is found as a function of overall heat dissipation of the chip including hotspot(s). As the goal is to keep the hottest point on the chip below certain threshold (e.g. 85°C), the result shows a dramatic reduction of the required total cooling power, when hybrid cooling scheme - superlattice hotspot cooler in conjunction with microchannel cooler - is used. Above particular analysis is based on the specific microchannel, but this proposed scheme allows us a systematic study to reduce the pump power further.
AB - We report theoretical investigation and optimization of a hot-spot cooling method. This hybrid scheme contains a liquid cooling microchannel and superlattice hotspot cooler(s). This analysis of the hybrid method aims to solve the potential thermal management challenges for hotspots especially in 3D stacked multichip packaging. The goal is to reduce the overall cooling power and optimize the energy efficiency. Starting with a generic modeling of the superlattice cooler system, the cooling temperature as a function of the superlattice thickness and the driving current is found. The analytic results are then compared with full 3D numerical simulation. The role of spreading thermal resistance in the chip substrate was found to be important. The later part of this report is the integration of the microchannel with the hotspot cooler. The pumping power is modeled based on the microchannel design and fluid properties. The total cooling power, the sum of the electrical power to pump the liquid and the electrical power to drive the superlattice cooler, is found as a function of overall heat dissipation of the chip including hotspot(s). As the goal is to keep the hottest point on the chip below certain threshold (e.g. 85°C), the result shows a dramatic reduction of the required total cooling power, when hybrid cooling scheme - superlattice hotspot cooler in conjunction with microchannel cooler - is used. Above particular analysis is based on the specific microchannel, but this proposed scheme allows us a systematic study to reduce the pump power further.
KW - cooling power
KW - energy efficient
KW - hotspot
KW - liquid cooling
KW - optimization
KW - superlattice micro cooler
UR - http://www.scopus.com/inward/record.url?scp=84866144420&partnerID=8YFLogxK
U2 - 10.1109/ITHERM.2012.6231419
DO - 10.1109/ITHERM.2012.6231419
M3 - Conference contribution
AN - SCOPUS:84866144420
SN - 9781424495320
T3 - InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM
SP - 99
EP - 106
BT - Proceedings of the 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2012
T2 - 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2012
Y2 - 30 May 2012 through 1 June 2012
ER -