Comparisons and improvements of designs of data slicers and clock synchronization circuits for broadcast teletext decoders operating in a multipath environment

It is shown that multipath propagation imposes a serious performance degradation on broadcast teletext systems designed according to the North American Basic Teletext Specifications (NABTS). By using both analysis and a comprehensive computer simulation model of the teletext broadcast system, it was found that very significant gains in performance could be obtained by improving slicing level and clock synchronization circuit designs. Several slicing level and clock synchronization (also called bit timing recovery (BTR)) circuits were modelled and simulated and their performances compared. These included peak detecting, averaging, modified averaging, adaptive and ideal slicers. The performance criterion used for assessing performance improvements was the probability of bit error at the output of the teletext receiver. Symbol synchronization circuits used in these simulations included zero-crossing and correlator-based BTR techniques. The averaging and adaptive slicers used with the correlator BTR circuit were found to give the best performance, but the complexity and cost of an adaptive Slicer reduce the advantages of system implementation. Error-correcting code performance is also improved by using a correlator BTR circuit.