TY - GEN
T1 - Comparing LLC-Memory Traffic between CPU and GPU Architectures
AU - Haque Monil, Mohammad Alaul
AU - Lee, Seyong
AU - Vetter, Jeffrey S.
AU - Malony, Allen D.
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - The cache hierarchy in modern CPUs and GPUs is becoming increasingly complex, which makes understanding the handshake between the memory access patterns and the cache hierarchy difficult. Moreover, the details of different cache policies are not publicly available. Therefore, the research community relies on observation to understand the relationship between memory access patterns and cache hierarchy. Our previous studies delved into the different microarchitectures of Intel CPUs. In this study, GPUs from NVIDIA and AMD are considered. Even though the execution models in CPUs and GPUs are distinct, this study attempts to correlate the behavior of the cache hierarchy of CPUs and GPUs. Using the knowledge gathered from studying Intel CPUs, the similarities and dissimilarities between CPUs and GPUs are identified. Through model evaluation, this study provides a proof of concept that traffic between last-level cache and memory can be predicted for sequential streaming and strided access patterns on GPUs.
AB - The cache hierarchy in modern CPUs and GPUs is becoming increasingly complex, which makes understanding the handshake between the memory access patterns and the cache hierarchy difficult. Moreover, the details of different cache policies are not publicly available. Therefore, the research community relies on observation to understand the relationship between memory access patterns and cache hierarchy. Our previous studies delved into the different microarchitectures of Intel CPUs. In this study, GPUs from NVIDIA and AMD are considered. Even though the execution models in CPUs and GPUs are distinct, this study attempts to correlate the behavior of the cache hierarchy of CPUs and GPUs. Using the knowledge gathered from studying Intel CPUs, the similarities and dissimilarities between CPUs and GPUs are identified. Through model evaluation, this study provides a proof of concept that traffic between last-level cache and memory can be predicted for sequential streaming and strided access patterns on GPUs.
KW - AMD
KW - GPU
KW - Intel
KW - Memory Access Pattern
KW - NVIDIA
UR - http://www.scopus.com/inward/record.url?scp=85124484031&partnerID=8YFLogxK
U2 - 10.1109/RSDHA54838.2021.00007
DO - 10.1109/RSDHA54838.2021.00007
M3 - Conference contribution
AN - SCOPUS:85124484031
T3 - Proceedings of RSDHA 2021: Redefining Scalability for Diversely Heterogeneous Architectures, Held in conjunction with SC 2021: The International Conference for High Performance Computing, Networking, Storage and Analysis
SP - 8
EP - 16
BT - Proceedings of RSDHA 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE/ACM Redefining Scalability for Diversely Heterogeneous Architectures, RSDHA 2021
Y2 - 19 November 2021
ER -