Abstract
The cache hierarchy in modern CPUs and GPUs is becoming increasingly complex, which makes understanding the handshake between the memory access patterns and the cache hierarchy difficult. Moreover, the details of different cache policies are not publicly available. Therefore, the research community relies on observation to understand the relationship between memory access patterns and cache hierarchy. Our previous studies delved into the different microarchitectures of Intel CPUs. In this study, GPUs from NVIDIA and AMD are considered. Even though the execution models in CPUs and GPUs are distinct, this study attempts to correlate the behavior of the cache hierarchy of CPUs and GPUs. Using the knowledge gathered from studying Intel CPUs, the similarities and dissimilarities between CPUs and GPUs are identified. Through model evaluation, this study provides a proof of concept that traffic between last-level cache and memory can be predicted for sequential streaming and strided access patterns on GPUs.
Original language | English |
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Title of host publication | Proceedings of RSDHA 2021 |
Subtitle of host publication | Redefining Scalability for Diversely Heterogeneous Architectures, Held in conjunction with SC 2021: The International Conference for High Performance Computing, Networking, Storage and Analysis |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 8-16 |
Number of pages | 9 |
ISBN (Electronic) | 9781665458771 |
DOIs | |
State | Published - 2021 |
Event | 2021 IEEE/ACM Redefining Scalability for Diversely Heterogeneous Architectures, RSDHA 2021 - St. Louis, United States Duration: Nov 19 2021 → … |
Publication series
Name | Proceedings of RSDHA 2021: Redefining Scalability for Diversely Heterogeneous Architectures, Held in conjunction with SC 2021: The International Conference for High Performance Computing, Networking, Storage and Analysis |
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Conference
Conference | 2021 IEEE/ACM Redefining Scalability for Diversely Heterogeneous Architectures, RSDHA 2021 |
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Country/Territory | United States |
City | St. Louis |
Period | 11/19/21 → … |
Funding
This research was supported by the following sources: (1) the US Department of Defense, Brisbane: Productive Programming Systems in the Era of Extremely Heterogeneous and Ephemeral Computer Architectures and (2) DOE Office of Science, Office of Advanced Scientific Computing Research, Scientific Discovery through Advanced Computing program. Notice: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (http://energy.gov/downloads/doe-public-access-plan).
Keywords
- AMD
- GPU
- Intel
- Memory Access Pattern
- NVIDIA