CMOS signal conditioning ASIC for large silicon pixels

J. Walter; C. Britton; E. Fairstein; F. W. Garber; M. Simpson

CMOS signal conditioning ASIC for large silicon pixels

J. Walter, C. Britton, E. Fairstein, F. W. Garber, M. Simpson

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

We designed, constructed, and tested a CMOS ASIC consisting of a preamplifier, shaping amplifier, and externally adjustable discriminator. This device was designed for detectors with reasonably fast rise times (compared to 1 μs) and capacitances in the range of 5 to 100 pF. The design was implemented with both PMOS and NMOS inputs. The NMOS version has a superior noise slope of 7 rms e/pF and an average noise at 6 pF input load of less than 375 rms electrons. The charge conversion sensitivity is 2.4 V/pC and the power drain is less than 10 mW/channel.

Original language	English
Pages	509-511
Number of pages	3
State	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) - Anaheim, CA, USA Duration: Nov 2 1996 → Nov 9 1996

Conference

Conference	Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)
City	Anaheim, CA, USA
Period	11/2/96 → 11/9/96

Cite this

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title = "CMOS signal conditioning ASIC for large silicon pixels",

abstract = "We designed, constructed, and tested a CMOS ASIC consisting of a preamplifier, shaping amplifier, and externally adjustable discriminator. This device was designed for detectors with reasonably fast rise times (compared to 1 μs) and capacitances in the range of 5 to 100 pF. The design was implemented with both PMOS and NMOS inputs. The NMOS version has a superior noise slope of 7 rms e/pF and an average noise at 6 pF input load of less than 375 rms electrons. The charge conversion sensitivity is 2.4 V/pC and the power drain is less than 10 mW/channel.",

author = "J. Walter and C. Britton and E. Fairstein and Garber, {F. W.} and M. Simpson",

year = "1996",

language = "English",

pages = "509--511",

note = "Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) ; Conference date: 02-11-1996 Through 09-11-1996",

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TY - CONF

T1 - CMOS signal conditioning ASIC for large silicon pixels

AU - Walter, J.

AU - Britton, C.

AU - Fairstein, E.

AU - Garber, F. W.

AU - Simpson, M.

PY - 1996

Y1 - 1996

N2 - We designed, constructed, and tested a CMOS ASIC consisting of a preamplifier, shaping amplifier, and externally adjustable discriminator. This device was designed for detectors with reasonably fast rise times (compared to 1 μs) and capacitances in the range of 5 to 100 pF. The design was implemented with both PMOS and NMOS inputs. The NMOS version has a superior noise slope of 7 rms e/pF and an average noise at 6 pF input load of less than 375 rms electrons. The charge conversion sensitivity is 2.4 V/pC and the power drain is less than 10 mW/channel.

AB - We designed, constructed, and tested a CMOS ASIC consisting of a preamplifier, shaping amplifier, and externally adjustable discriminator. This device was designed for detectors with reasonably fast rise times (compared to 1 μs) and capacitances in the range of 5 to 100 pF. The design was implemented with both PMOS and NMOS inputs. The NMOS version has a superior noise slope of 7 rms e/pF and an average noise at 6 pF input load of less than 375 rms electrons. The charge conversion sensitivity is 2.4 V/pC and the power drain is less than 10 mW/channel.

UR - http://www.scopus.com/inward/record.url?scp=0030358535&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0030358535

SP - 509

EP - 511

T2 - Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)

Y2 - 2 November 1996 through 9 November 1996

ER -

CMOS signal conditioning ASIC for large silicon pixels

Abstract

Conference

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