Challenges Designing for FPGAs Using High-Level Synthesis

Clayton J. Faber; Steven D. Harris; Zhili Xiac; Roger D. Chamberlain; Anthony M. Cabrera

doi:10.1109/HPEC55821.2022.9926398

Challenges Designing for FPGAs Using High-Level Synthesis

Clayton J. Faber, Steven D. Harris, Zhili Xiac, Roger D. Chamberlain, Anthony M. Cabrera

Architectures and Performance

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

High-Level Synthesis (HLS) tools are aimed at enabling performant FPGA designs that are authored in a high-level language. While commercial HLS tools are available today, there is still a substantial performance gap between most designs developed via HLS relative to traditional, labor intensive approaches. We report on several cases where an anticipated performance improvement was either not realized or resulted in decreased performance. These include: programming paradigm choices between data parallel vs. pipelined designs; dataflow implementations; configuration parameter choices; and handling odd data set sizes. The results point to a number of improvements that are needed for HLS tool flows, including a strong need for performance modeling that can reliably guide the compilation optimization process.

Original language	English
Title of host publication	2022 IEEE High Performance Extreme Computing Conference, HPEC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665497862
DOIs	https://doi.org/10.1109/HPEC55821.2022.9926398
State	Published - 2022
Event	2022 IEEE High Performance Extreme Computing Conference, HPEC 2022 - Virtual, Online, United States Duration: Sep 19 2022 → Sep 23 2022

Publication series

Name	2022 IEEE High Performance Extreme Computing Conference, HPEC 2022

Conference

Conference	2022 IEEE High Performance Extreme Computing Conference, HPEC 2022
Country/Territory	United States
City	Virtual, Online
Period	09/19/22 → 09/23/22

Funding

This work was supported by NSF awards CNS-1763503 and CNS-1814739, the DARPA MTO Domain-Specific System-on-Chip program, and the DoE ASCR program. ACKNOWLEDGEMENTS This manuscript has been co-authored by UT-Battelle, LLC under Contract No. DE-AC05-00OR22725 with the U.S. Department of Energy. The U.S. Government retains and the publisher, by accepting the article for publication, acknowledges that the U.S. Government retains a non-exclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for U.S. Government purposes. The Department of Energy will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (available at http://energy.gov/downloads/doe-public-access-plan).

Keywords

FPGA
Field-Programmable Gate Array
HLS
High-Level Synthesis

Access to Document

10.1109/HPEC55821.2022.9926398

Cite this

Faber, C. J., Harris, S. D., Xiac, Z., Chamberlain, R. D., & Cabrera, A. M. (2022). Challenges Designing for FPGAs Using High-Level Synthesis. In 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022 (2022 IEEE High Performance Extreme Computing Conference, HPEC 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPEC55821.2022.9926398

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title = "Challenges Designing for FPGAs Using High-Level Synthesis",

abstract = "High-Level Synthesis (HLS) tools are aimed at enabling performant FPGA designs that are authored in a high-level language. While commercial HLS tools are available today, there is still a substantial performance gap between most designs developed via HLS relative to traditional, labor intensive approaches. We report on several cases where an anticipated performance improvement was either not realized or resulted in decreased performance. These include: programming paradigm choices between data parallel vs. pipelined designs; dataflow implementations; configuration parameter choices; and handling odd data set sizes. The results point to a number of improvements that are needed for HLS tool flows, including a strong need for performance modeling that can reliably guide the compilation optimization process.",

keywords = "FPGA, Field-Programmable Gate Array, HLS, High-Level Synthesis",

author = "Faber, {Clayton J.} and Harris, {Steven D.} and Zhili Xiac and Chamberlain, {Roger D.} and Cabrera, {Anthony M.}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022 ; Conference date: 19-09-2022 Through 23-09-2022",

year = "2022",

doi = "10.1109/HPEC55821.2022.9926398",

language = "English",

series = "2022 IEEE High Performance Extreme Computing Conference, HPEC 2022",

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Faber, CJ, Harris, SD, Xiac, Z, Chamberlain, RD & Cabrera, AM 2022, Challenges Designing for FPGAs Using High-Level Synthesis. in 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022. 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022, Institute of Electrical and Electronics Engineers Inc., 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022, Virtual, Online, United States, 09/19/22. https://doi.org/10.1109/HPEC55821.2022.9926398

Challenges Designing for FPGAs Using High-Level Synthesis. / Faber, Clayton J.; Harris, Steven D.; Xiac, Zhili et al.
2022 IEEE High Performance Extreme Computing Conference, HPEC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 IEEE High Performance Extreme Computing Conference, HPEC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - High-Level Synthesis (HLS) tools are aimed at enabling performant FPGA designs that are authored in a high-level language. While commercial HLS tools are available today, there is still a substantial performance gap between most designs developed via HLS relative to traditional, labor intensive approaches. We report on several cases where an anticipated performance improvement was either not realized or resulted in decreased performance. These include: programming paradigm choices between data parallel vs. pipelined designs; dataflow implementations; configuration parameter choices; and handling odd data set sizes. The results point to a number of improvements that are needed for HLS tool flows, including a strong need for performance modeling that can reliably guide the compilation optimization process.

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Challenges Designing for FPGAs Using High-Level Synthesis

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