TY - GEN
T1 - Balancing FPGA resource utilities
AU - Liang, Xuejun
AU - Vetter, Jeffrey S.
AU - Smith, Melissa C.
AU - Bland, Arthur S.
PY - 2005
Y1 - 2005
N2 - Balancing the use of FGPA resources such as FPGA slices, block RAMs, and block multipliers is desirable in many FPGA applications. This task can be carried out manually by experienced hardware designers with the use of hardware description languages, such as Verilog and VHDL. However, many users of reconfigurable computers are software developers who depend on hardware synthesis tools or even high-level synthesis tools to deal with the details beneath the application logic. In this paper, a motivating example of balancing FPGA resource utilities is given first. A module selection optimization problem is then formulated, in which, balancing FPGA resource utilities is treated as a constraint, so that the solution to the module selection problem is the balanced use of the FPGA resources. Several variations of the problem formulation are discussed. A naïve algorithm and an efficient greedy algorithm to solve the problem are provided and compared. Some experimental results are also presented.
AB - Balancing the use of FGPA resources such as FPGA slices, block RAMs, and block multipliers is desirable in many FPGA applications. This task can be carried out manually by experienced hardware designers with the use of hardware description languages, such as Verilog and VHDL. However, many users of reconfigurable computers are software developers who depend on hardware synthesis tools or even high-level synthesis tools to deal with the details beneath the application logic. In this paper, a motivating example of balancing FPGA resource utilities is given first. A module selection optimization problem is then formulated, in which, balancing FPGA resource utilities is treated as a constraint, so that the solution to the module selection problem is the balanced use of the FPGA resources. Several variations of the problem formulation are discussed. A naïve algorithm and an efficient greedy algorithm to solve the problem are provided and compared. Some experimental results are also presented.
KW - FPGA
KW - High-level synthesis
KW - Module selection
KW - Reconfigurable computing
UR - http://www.scopus.com/inward/record.url?scp=60749098546&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:60749098546
SN - 9781932415742
T3 - Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05
SP - 156
EP - 162
BT - Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05
T2 - 2005 5th International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05
Y2 - 27 June 2005 through 30 June 2005
ER -