Abstract
Recently, researchers have explored way-based hybrid SRAM-NVM (non-volatile memory) last level caches (LLCs) to bring the best of SRAM and NVM together. However, the limited write endurance of NVMs restricts the lifetime of these hybrid caches. We present AYUSH, a technique to enhance the lifetime of hybrid caches, which works by using data-migration to preferentially use SRAM for storing frequently-reused data. Microarchitectural simulations confirm that AYUSH achieves larger improvement in lifetime than a previous technique and also maintains performance and energy efficiency. For single, dual and quad-core workloads, the average increase in cache lifetime with AYUSH is 6.90, 24.06 and 47.62×, respectively.
Original language | English |
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Article number | 6892940 |
Pages (from-to) | 115-118 |
Number of pages | 4 |
Journal | IEEE Computer Architecture Letters |
Volume | 14 |
Issue number | 2 |
DOIs | |
State | Published - Jul 1 2015 |
Keywords
- Non-volatile memory (NVM)
- SRAM-NVM cache
- device lifetime
- hybrid cache
- write endurance