TY - GEN
T1 - Autotuning FPGA design parameters for performance and power
AU - Mametjanov, Azamat
AU - Balaprakash, Prasanna
AU - Choudary, Chekuri
AU - Hovland, Paul D.
AU - Wild, Stefan M.
AU - Sabin, Gerald
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/15
Y1 - 2015/7/15
N2 - Many factors affect the performance and power characteristics of FPGA designs. Among them are the optimization parameters for synthesis, map, and place-and-route design tools. Choosing the right combination of these parameters can substantially lower power requirements, while still satisfying timing constraints. Finding such an improvement, however, requires significant experimentation by the FPGA designer. Exhaustive search through the parameter space is an automated alternative to experimentation but is intractable because of the large search space and the long build time of each parameter combination. In this paper, we propose a machine-learning-based approach to tune FPGA design parameters. It performs sampling-based reduction of the parameter space and guides the search toward promising parameter configurations. In our experiments, such selective sampling finds parameter configurations that meet the timing constraints and are within 0.2% of the optimal power consumption. Furthermore, these configurations are found in an order of magnitude less time compared with exhaustive search. Such speedups can substantially alleviate bottlenecks in the FPGA design process.
AB - Many factors affect the performance and power characteristics of FPGA designs. Among them are the optimization parameters for synthesis, map, and place-and-route design tools. Choosing the right combination of these parameters can substantially lower power requirements, while still satisfying timing constraints. Finding such an improvement, however, requires significant experimentation by the FPGA designer. Exhaustive search through the parameter space is an automated alternative to experimentation but is intractable because of the large search space and the long build time of each parameter combination. In this paper, we propose a machine-learning-based approach to tune FPGA design parameters. It performs sampling-based reduction of the parameter space and guides the search toward promising parameter configurations. In our experiments, such selective sampling finds parameter configurations that meet the timing constraints and are within 0.2% of the optimal power consumption. Furthermore, these configurations are found in an order of magnitude less time compared with exhaustive search. Such speedups can substantially alleviate bottlenecks in the FPGA design process.
KW - Field programmable gate arrays
KW - Optimal design and tuning
KW - Power optimization
KW - Tuned circuits
UR - http://www.scopus.com/inward/record.url?scp=84943378377&partnerID=8YFLogxK
U2 - 10.1109/FCCM.2015.54
DO - 10.1109/FCCM.2015.54
M3 - Conference contribution
AN - SCOPUS:84943378377
T3 - Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
SP - 84
EP - 91
BT - Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
Y2 - 3 May 2015 through 5 May 2015
ER -