Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices

Mark Gates; Jakub Kurzak; Piotr Luszczek; Yu Pei; Jack Dongarra

doi:10.1109/IPDPSW.2017.18

Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices

Mark Gates, Jakub Kurzak, Piotr Luszczek, Yu Pei, Jack Dongarra

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

Batch matrix operations address the case of solving the same linear algebra problem for a very large number of very small matrices. In this paper, we focus on implementing the batch Cholesky factorization in CUDA, in single precision arithmetic, for NVIDIA GPUs. Specifically, we look into the benefits of using noncanonical data layouts, where consecutive memory locations store elements with the same row and column index in a set of consecutive matrices. We discuss a number of different implementation options and tuning parameters. We demonstrate superior performance to traditional implementations for the case of very small matrices.

Original language	English
Title of host publication	Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1408-1417
Number of pages	10
ISBN (Electronic)	9781538634080
DOIs	https://doi.org/10.1109/IPDPSW.2017.18
State	Published - Jun 30 2017
Externally published	Yes
Event	31st IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017 - Orlando, United States Duration: May 29 2017 → Jun 2 2017

Publication series

Name	Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017

Conference

Conference	31st IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017
Country/Territory	United States
City	Orlando
Period	05/29/17 → 06/2/17

Funding

Autotuning of Computational Kernels” from the National Science Foundation.

Keywords

Cholesky factorization
GPU computing
batch computation
data layout
numerical linear algebra

Access to Document

10.1109/IPDPSW.2017.18

Cite this

Gates, M., Kurzak, J., Luszczek, P., Pei, Y., & Dongarra, J. (2017). Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices. In Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017 (pp. 1408-1417). Article 7965201 (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPSW.2017.18

Gates, Mark ; Kurzak, Jakub ; Luszczek, Piotr et al. / Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices. Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1408-1417 (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017).

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title = "Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices",

abstract = "Batch matrix operations address the case of solving the same linear algebra problem for a very large number of very small matrices. In this paper, we focus on implementing the batch Cholesky factorization in CUDA, in single precision arithmetic, for NVIDIA GPUs. Specifically, we look into the benefits of using noncanonical data layouts, where consecutive memory locations store elements with the same row and column index in a set of consecutive matrices. We discuss a number of different implementation options and tuning parameters. We demonstrate superior performance to traditional implementations for the case of very small matrices.",

keywords = "Cholesky factorization, GPU computing, batch computation, data layout, numerical linear algebra",

author = "Mark Gates and Jakub Kurzak and Piotr Luszczek and Yu Pei and Jack Dongarra",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 31st IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017 ; Conference date: 29-05-2017 Through 02-06-2017",

year = "2017",

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doi = "10.1109/IPDPSW.2017.18",

language = "English",

series = "Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017",

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Gates, M, Kurzak, J, Luszczek, P, Pei, Y & Dongarra, J 2017, Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices. in Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017., 7965201, Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017, Institute of Electrical and Electronics Engineers Inc., pp. 1408-1417, 31st IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017, Orlando, United States, 05/29/17. https://doi.org/10.1109/IPDPSW.2017.18

Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices. / Gates, Mark; Kurzak, Jakub; Luszczek, Piotr et al.
Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1408-1417 7965201 (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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PY - 2017/6/30

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N2 - Batch matrix operations address the case of solving the same linear algebra problem for a very large number of very small matrices. In this paper, we focus on implementing the batch Cholesky factorization in CUDA, in single precision arithmetic, for NVIDIA GPUs. Specifically, we look into the benefits of using noncanonical data layouts, where consecutive memory locations store elements with the same row and column index in a set of consecutive matrices. We discuss a number of different implementation options and tuning parameters. We demonstrate superior performance to traditional implementations for the case of very small matrices.

AB - Batch matrix operations address the case of solving the same linear algebra problem for a very large number of very small matrices. In this paper, we focus on implementing the batch Cholesky factorization in CUDA, in single precision arithmetic, for NVIDIA GPUs. Specifically, we look into the benefits of using noncanonical data layouts, where consecutive memory locations store elements with the same row and column index in a set of consecutive matrices. We discuss a number of different implementation options and tuning parameters. We demonstrate superior performance to traditional implementations for the case of very small matrices.

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KW - GPU computing

KW - batch computation

KW - data layout

KW - numerical linear algebra

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Gates M, Kurzak J, Luszczek P, Pei Y, Dongarra J. Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices. In Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1408-1417. 7965201. (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017). doi: 10.1109/IPDPSW.2017.18

Autotuning batch cholesky factorization in CUDA with interleaved layout of matrices

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