Architecting SOT-RAM Based GPU Register File

Sparsh Mittal; Rajendra Bishnoi; Fabian Oboril; Haonan Wang; Mehdi Tahoori; Adwait Jog; Jeffrey S. Vetter

doi:10.1109/ISVLSI.2017.17

Architecting SOT-RAM Based GPU Register File

Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Tahoori, Adwait Jog, Jeffrey S. Vetter

Computer Science and Mathematics Div

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.

Original language	English
Title of host publication	Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Editors	Ricardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
Publisher	IEEE Computer Society
Pages	38-44
Number of pages	7
ISBN (Electronic)	9781509067626
DOIs	https://doi.org/10.1109/ISVLSI.2017.17
State	Published - Jul 20 2017
Event	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: Jul 3 2017 → Jul 5 2017

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2017-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Country/Territory	Germany
City	Bochum, North Rhine-Westfalia
Period	07/3/17 → 07/5/17

Funding

Support for this work was provided by SERB ECR/2017/000622 project (India), DOE ASCR, NSF grant CCF 1657336 and a start-up grant from College of William and Mary (USA).

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISVLSI.2017.17

Cite this

Mittal, S., Bishnoi, R., Oboril, F., Wang, H., Tahoori, M., Jog, A., & Vetter, J. S. (2017). Architecting SOT-RAM Based GPU Register File. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 38-44). Article 7987492 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.17

Mittal, Sparsh ; Bishnoi, Rajendra ; Oboril, Fabian et al. / Architecting SOT-RAM Based GPU Register File. Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. editor / Ricardo Reis ; Mircea Stan ; Michael Huebner ; Nikolaos Voros. IEEE Computer Society, 2017. pp. 38-44 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).

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title = "Architecting SOT-RAM Based GPU Register File",

abstract = "With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.",

author = "Sparsh Mittal and Rajendra Bishnoi and Fabian Oboril and Haonan Wang and Mehdi Tahoori and Adwait Jog and Vetter, {Jeffrey S.}",

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Mittal, S, Bishnoi, R, Oboril, F, Wang, H, Tahoori, M, Jog, A & Vetter, JS 2017, Architecting SOT-RAM Based GPU Register File. in R Reis, M Stan, M Huebner & N Voros (eds), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017., 7987492, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2017-July, IEEE Computer Society, pp. 38-44, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 07/3/17. https://doi.org/10.1109/ISVLSI.2017.17

Architecting SOT-RAM Based GPU Register File. / Mittal, Sparsh; Bishnoi, Rajendra; Oboril, Fabian et al.
Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. ed. / Ricardo Reis; Mircea Stan; Michael Huebner; Nikolaos Voros. IEEE Computer Society, 2017. p. 38-44 7987492 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Vetter, Jeffrey S.

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N2 - With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.

AB - With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.

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Mittal S, Bishnoi R, Oboril F, Wang H, Tahoori M, Jog A et al. Architecting SOT-RAM Based GPU Register File. In Reis R, Stan M, Huebner M, Voros N, editors, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. IEEE Computer Society. 2017. p. 38-44. 7987492. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/ISVLSI.2017.17

Architecting SOT-RAM Based GPU Register File

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UN SDGs

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