TY - GEN
T1 - Analyzing suitability of contemporary 3D stacked PIM architectures for HPC scientific applications
AU - Peng, Ivy B.
AU - Vetter, Jeffrey S.
AU - Moore, Shirley
AU - Joydeep, Rakshit
AU - Markidis, Stefano
N1 - Publisher Copyright:
© 2019 Association for Computing Machinery.
PY - 2019/4/30
Y1 - 2019/4/30
N2 - Scaling off-chip bandwidth is challenging due to fundamental limitations, such as a fixed pin count and plateauing signaling rates. Recently, vendors have turned to 2.5D and 3D stacking to closely integrate system components. Interestingly, these technologies can integrate a logic layer under multiple memory dies, enabling computing capability inside a memory stack. This trend in stacking is making PIM architectures commercially viable. In this work, we investigate the suitability of offloading kernels in scientific applications onto 3D stacked PIM architectures. We evaluate several hardware constraints resulted from the stacked structure. We perform extensive simulation experiments and in-depth analysis to quantify the impact of application locality in TLBs, data caches, and memory stacks. Our results also identify design optimization areas in software and hardware for HPC scientific applications.
AB - Scaling off-chip bandwidth is challenging due to fundamental limitations, such as a fixed pin count and plateauing signaling rates. Recently, vendors have turned to 2.5D and 3D stacking to closely integrate system components. Interestingly, these technologies can integrate a logic layer under multiple memory dies, enabling computing capability inside a memory stack. This trend in stacking is making PIM architectures commercially viable. In this work, we investigate the suitability of offloading kernels in scientific applications onto 3D stacked PIM architectures. We evaluate several hardware constraints resulted from the stacked structure. We perform extensive simulation experiments and in-depth analysis to quantify the impact of application locality in TLBs, data caches, and memory stacks. Our results also identify design optimization areas in software and hardware for HPC scientific applications.
KW - 3D Stacked Memory
KW - PIM
KW - Processing-In-Memory
UR - http://www.scopus.com/inward/record.url?scp=85066055698&partnerID=8YFLogxK
U2 - 10.1145/3310273.3322831
DO - 10.1145/3310273.3322831
M3 - Conference contribution
AN - SCOPUS:85066055698
T3 - ACM International Conference on Computing Frontiers 2019, CF 2019 - Proceedings
SP - 256
EP - 262
BT - ACM International Conference on Computing Frontiers 2019, CF 2019 - Proceedings
PB - Association for Computing Machinery, Inc
T2 - 16th ACM International Conference on Computing Frontiers, CF 2019
Y2 - 30 April 2019 through 2 May 2019
ER -