TY - GEN
T1 - Analysis in performance and new model for multiple kernels executions on many-core architectures
AU - Valero-Lara, Pedro
AU - Pelayo, Fernando L.
PY - 2013
Y1 - 2013
N2 - Nowadays, due to massively parallel characteristics of current many-core architectures, these devices are not only being used in order to exploit data-parallelism and to minimize the execution time in a single problem, but, they are beginning to be used in order both to execute and to increase the performances when executing more than one application simultaneously. In this work, we provide a performance analysis on the use of current many-core architectures for this new purpose; this performance analysis has been carried out over two different many-core architectures. Furthermore, two different programming approaches to tackle this new role have been tested. The results so obtained show that a increase in the computational requirements implies an important fall in performance. The main objective of this paper is to explain the reasons for this behavior, and afterwards, to propose a set of alternatives to deal with these disadvantages previously mentioned.
AB - Nowadays, due to massively parallel characteristics of current many-core architectures, these devices are not only being used in order to exploit data-parallelism and to minimize the execution time in a single problem, but, they are beginning to be used in order both to execute and to increase the performances when executing more than one application simultaneously. In this work, we provide a performance analysis on the use of current many-core architectures for this new purpose; this performance analysis has been carried out over two different many-core architectures. Furthermore, two different programming approaches to tackle this new role have been tested. The results so obtained show that a increase in the computational requirements implies an important fall in performance. The main objective of this paper is to explain the reasons for this behavior, and afterwards, to propose a set of alternatives to deal with these disadvantages previously mentioned.
KW - CUDA
KW - Heterogeneous architectures
KW - Multiple kernels execution
UR - http://www.scopus.com/inward/record.url?scp=84889026220&partnerID=8YFLogxK
U2 - 10.1109/ICCI-CC.2013.6622243
DO - 10.1109/ICCI-CC.2013.6622243
M3 - Conference contribution
AN - SCOPUS:84889026220
SN - 9781479907816
T3 - Proceedings of the 12th IEEE International Conference on Cognitive Informatics and Cognitive Computing, ICCI*CC 2013
SP - 189
EP - 194
BT - Proceedings of the 12th IEEE International Conference on Cognitive Informatics and Cognitive Computing, ICCI*CC 2013
T2 - 12th IEEE International Conference on Cognitive Informatics and Cognitive Computing, ICCI*CC 2013
Y2 - 16 July 2013 through 18 July 2013
ER -