Abstract
Middle-point inductance {{\boldsymbol L}-{{\boldsymbol {\text{middle}}}}} can be introduced in multiple-chip power module package designs. In this paper, the effect of middle-point inductance on switching transients is analyzed first using a frequency-domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying {{\boldsymbol L}-{{\boldsymbol {\text{middle}}}}}, and extensive switching tests are conducted to evaluate the middle-point inductance's impact. Experiment result shows that the active mosfet's turn-on loss decreases at higher values of {{\boldsymbol L}-{{\boldsymbol {\text{middle}}}}}, while its turn-off loss increases. Detailed analysis of this loss variation is presented. In addition to the switching loss variation, it is also observed that different peak voltage stresses are imposed on the active switch and antiparallel diode during the switching transients. Specifically, in the case of lower mosfet's turn-off, the maximum voltage of the lower mosfet increases as {{\boldsymbol L}-{{\boldsymbol {\text{middle}}}}} goes up; however, the peak voltage of the antiparallel diode decreases significantly. The induced voltage spikes during upper mosfet turn-on process is also evaluated, and an opposite trend is observed experimentally. Analysis of the voltage overshoot variation is discussed. Based on the experimental evaluation and analysis, a multiple-chip power module package design guideline is summarized considering the middle-point inductance's effect.
Original language | English |
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Article number | 8501602 |
Pages (from-to) | 6613-6627 |
Number of pages | 15 |
Journal | IEEE Transactions on Power Electronics |
Volume | 34 |
Issue number | 7 |
DOIs | |
State | Published - Jul 2019 |
Bibliographical note
Publisher Copyright:© 1986-2012 IEEE.
Keywords
- Middle-point parasitic inductance
- Power module package
- Silicon carbide (SiC) MOSFETs
- Split converter
- Switching transients