Abstract
Deep Machine Learning (DML) algorithms have proven to be highly successful at challenging, high-dimensional learning problems, but their widespread deployment is limited by their heavy computational requirements and the associated power consumption. Analog computational circuits offer the potential for large improvements in power efficiency, but noise, mismatch, and other effects cause deviations from ideal computations. In this paper we describe circuits useful for DML algorithms, including a tunable-width bump circuit and a configurable distance calculator. We also discuss the impacts of computational errors on learning performance. Finally we will describe a complete deep learning engine implemented using current-mode analog circuits and compare its performance to digital equivalents.
Original language | English |
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Title of host publication | IEEE Biomedical Circuits and Systems Conference |
Subtitle of host publication | Engineering for Healthy Minds and Able Bodies, BioCAS 2015 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781479972333 |
DOIs | |
State | Published - Dec 4 2015 |
Externally published | Yes |
Event | 11th IEEE Biomedical Circuits and Systems Conference, BioCAS 2015 - Atlanta, United States Duration: Oct 22 2015 → Oct 24 2015 |
Publication series
Name | IEEE Biomedical Circuits and Systems Conference: Engineering for Healthy Minds and Able Bodies, BioCAS 2015 - Proceedings |
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Conference
Conference | 11th IEEE Biomedical Circuits and Systems Conference, BioCAS 2015 |
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Country/Territory | United States |
City | Atlanta |
Period | 10/22/15 → 10/24/15 |
Funding
This work was partially supported by the NSF SHF program through grant #CCF-1218492 and by the DARPA UPSIDE project through agreement #HR0011-13-2-0016.
Keywords
- analog CMOS
- deep learning
- error modeling
- neuromorphic computing