Abstract
In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the other two memory technologies. We discuss the design and the signal communication framework through the STT-RAM crossbar array for training and inference in SNNs. Each STT-RAM cell in the array stores a single bit value. Our neurosynaptic computational core consists of the memory crossbar array and its read/write peripheral circuitry and the digital logic for the spiking neurons, weight update computations, spike router, and decoder for incoming spike packets. Our STT-RAM based design shows ~20× higher performance per unit Watt per unit area compared to conventional SRAM based design, making it a promising learning platform for realizing systems with significant area and power limitations.
Original language | English |
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Title of host publication | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 |
Editors | Giorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1019-1024 |
Number of pages | 6 |
ISBN (Electronic) | 9783981926347 |
DOIs | |
State | Published - Mar 2020 |
Externally published | Yes |
Event | 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France Duration: Mar 9 2020 → Mar 13 2020 |
Publication series
Name | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 |
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Conference
Conference | 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 |
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Country/Territory | France |
City | Grenoble |
Period | 03/9/20 → 03/13/20 |
Funding
This work was supported in part by the Semiconductor Research Corporation and Cisco.
Keywords
- Neuromorphic hardware
- STT-RAM
- Spiking Neural Networks
- crossbar arrays