TY - GEN
T1 - An FPGA-Based Neuromorphic Processor with All-to-All Connectivity
AU - Maheshwari, Disha
AU - Young, Aaron
AU - Date, Prasanna
AU - Kulkarni, Shruti
AU - Witherspoon, Brett
AU - Miniskar, Narsinga Rao
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Neuromorphic computing is a promising paradigm for future energy-efficient computing. At present, however, it is in its nascent stages - most hardware implementations are research-grade, commercial products are not available, and the software tools are not production-ready. The lack of hardware and software tools makes neuromorphic computing inaccessible to researchers around the globe. To this extent, we intend to build a low-cost, open-source, FPGA-based digital neuromorphic processor that can be used by researchers worldwide. In this paper, we present a preliminary implementation of the processor on a Xilinx Artix-7 FPGA using SystemVerilog. Our implementation supports the integrate-and-fire neuron with two parameters each for neurons and synapses. It also features all-to-all connectivity among neurons on the hardware. We test our implementation on four cases: bars and stripes datasets, shortest path algorithm, logic gates, and 8-3 encoder. We also perform a scalability study to understand the resource utilization of the FPGA as the number of all-to-all connected neurons increases. With our implementation, the Artix- 7 supports 65 neurons with all-to-all connectivity. Moreover, all the test cases mentioned above achieve 100% accuracy.
AB - Neuromorphic computing is a promising paradigm for future energy-efficient computing. At present, however, it is in its nascent stages - most hardware implementations are research-grade, commercial products are not available, and the software tools are not production-ready. The lack of hardware and software tools makes neuromorphic computing inaccessible to researchers around the globe. To this extent, we intend to build a low-cost, open-source, FPGA-based digital neuromorphic processor that can be used by researchers worldwide. In this paper, we present a preliminary implementation of the processor on a Xilinx Artix-7 FPGA using SystemVerilog. Our implementation supports the integrate-and-fire neuron with two parameters each for neurons and synapses. It also features all-to-all connectivity among neurons on the hardware. We test our implementation on four cases: bars and stripes datasets, shortest path algorithm, logic gates, and 8-3 encoder. We also perform a scalability study to understand the resource utilization of the FPGA as the number of all-to-all connected neurons increases. With our implementation, the Artix- 7 supports 65 neurons with all-to-all connectivity. Moreover, all the test cases mentioned above achieve 100% accuracy.
KW - Design Automation
KW - FPGA
KW - Neuromorphic Computing
KW - Neuromorphic Hardware
UR - http://www.scopus.com/inward/record.url?scp=85184832709&partnerID=8YFLogxK
U2 - 10.1109/ICRC60800.2023.10386808
DO - 10.1109/ICRC60800.2023.10386808
M3 - Conference contribution
AN - SCOPUS:85184832709
T3 - 2023 IEEE International Conference on Rebooting Computing, ICRC 2023
BT - 2023 IEEE International Conference on Rebooting Computing, ICRC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th IEEE International Conference on Rebooting Computing, ICRC 2023
Y2 - 5 December 2023 through 6 December 2023
ER -