An audio clock regenerator with a wide dividing ratio for HDMI

Seung Wuk Oh; Sang Ho Kim; Jin Ku Kang

doi:10.1109/ISCAS.2012.6271676

An audio clock regenerator with a wide dividing ratio for HDMI

Seung Wuk Oh, Sang Ho Kim, Jin Ku Kang

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

This paper presents a clock regenerator using two 2nd order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. The source device sends N (Dividing ratio of video clock to TMDS clock) and CTS (Cycle Time Stamp) values to the sink device for regenerating the audio clock. By processing the integer and fractional part of the N and CTS values separately at two different Σ-Δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard and occupies small chip area. The circuit is fabricated using 0.18um CMOS and shows 13mW power consumption with on-chip loop filter.

Original language	English
Pages	2019-2022
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271676
State	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	05/20/12 → 05/23/12

Access to Document

10.1109/ISCAS.2012.6271676

Cite this

@conference{23891c9a6d04408890d013c87551790a,

title = "An audio clock regenerator with a wide dividing ratio for HDMI",

abstract = "This paper presents a clock regenerator using two 2nd order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. The source device sends N (Dividing ratio of video clock to TMDS clock) and CTS (Cycle Time Stamp) values to the sink device for regenerating the audio clock. By processing the integer and fractional part of the N and CTS values separately at two different Σ-Δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard and occupies small chip area. The circuit is fabricated using 0.18um CMOS and shows 13mW power consumption with on-chip loop filter.",

author = "Oh, {Seung Wuk} and Kim, {Sang Ho} and Kang, {Jin Ku}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271676",

language = "English",

pages = "2019--2022",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - An audio clock regenerator with a wide dividing ratio for HDMI

AU - Oh, Seung Wuk

AU - Kim, Sang Ho

AU - Kang, Jin Ku

PY - 2012

Y1 - 2012

N2 - This paper presents a clock regenerator using two 2nd order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. The source device sends N (Dividing ratio of video clock to TMDS clock) and CTS (Cycle Time Stamp) values to the sink device for regenerating the audio clock. By processing the integer and fractional part of the N and CTS values separately at two different Σ-Δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard and occupies small chip area. The circuit is fabricated using 0.18um CMOS and shows 13mW power consumption with on-chip loop filter.

AB - This paper presents a clock regenerator using two 2nd order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. The source device sends N (Dividing ratio of video clock to TMDS clock) and CTS (Cycle Time Stamp) values to the sink device for regenerating the audio clock. By processing the integer and fractional part of the N and CTS values separately at two different Σ-Δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard and occupies small chip area. The circuit is fabricated using 0.18um CMOS and shows 13mW power consumption with on-chip loop filter.

UR - http://www.scopus.com/inward/record.url?scp=84866635159&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271676

DO - 10.1109/ISCAS.2012.6271676

M3 - Paper

AN - SCOPUS:84866635159

SP - 2019

EP - 2022

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

An audio clock regenerator with a wide dividing ratio for HDMI

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this