An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing

This letter presents a 20 Gb/s/pin single-ended PAM-4 transceiver implemented in an 8nm CMOS process, featuring an advanced switching jitter compensation (SWJC) technique and a DQS-driven amplifier bias generation method for a source-synchronous clocking system, aimed for next-generation low-power memory interfaces utilizing multi-level signaling. The proposed pre-channel SWJC (pre-SWJC) in the transmitter adjusts the input edge timing of the thermometer PAM-4 driver to control the transitions of the PAM-4 signal. This transition control advances the outermost transitions, thereby not only minimizing the switching jitter (SWJ) of the middle eye but also enhancing the effectiveness of the post-channel SWJC (post-SWJC) performed at the receiver. Ultimately, the comprehensive solution combining the proposed pre/post-SWJC improved the timing margin from 0.26 UI to 0.39 UI at a BER of 1e-12, with only a 4.5% increase in power consumption and a 0.59% area overhead. Additionally, the proposed DQS-driven biasing technique in the receiver supplies biases for the amplifiers in the data lanes by utilizing the common-mode feedback of the replica amplifier in the differential clock lane. This approach reduces variation sources compared to the self-biasing structure that uses common-mode feedback in the data lanes, thereby improving the standard deviation of the amplifier's bias voltage and gain variation by 58.3%.