An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing

A multi-bit third-order hybrid ΔΣ ADC is presented. The ADC obviates the need for dynamic element matching (DEM) in the critical feedback path, eliminating the systematic boundary of high clock frequency. This implementation incorporates continuous-time integrators in the first two stages to reduced power consumption, and a discrete-time integrator in the last stage to mitigate excess loop delay and quantizer sampling timing problem. The duty-cycle based Switched-R-MOSFET-C (SRMC) tuning employed in the design also helps to absorb finite opamp bandwidth/delay as well as frequency scalability. The proposed ΔΣ ADC is capable of converting up to +2 dBFS input without pole optimization. The 65nm CMOS implementation achieves 68 dB DR, 65 dB SNR, 64 dB SNDR, and 84 dB SFDR, while consuming 11 mW at 100 MHz clock and 16X OSR.