@inbook{77ad1d5c559b41909ba3cd7b5282f25b,
title = "Accurate cache and TLB characterization using hardware counters",
abstract = "We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.",
author = "Jack Dongarra and Shirley Moore and Philip Mucci and Keith Seymour and Haihang You",
year = "2004",
doi = "10.1007/978-3-540-24688-6_57",
language = "English",
isbn = "3540221166",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "432--439",
editor = "Marian Bubak and {van Albada}, {Geert Dick} and Sloot, {Peter M. A.} and Dongarra, {Jack J.}",
booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
}