Accurate cache and TLB characterization using hardware counters

Jack Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

13 Scopus citations

Abstract

We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsMarian Bubak, Geert Dick van Albada, Peter M. A. Sloot, Jack J. Dongarra
PublisherSpringer Verlag
Pages432-439
Number of pages8
ISBN (Print)3540221166
DOIs
StatePublished - 2004
Externally publishedYes

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3038
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

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