Accelerating scientific applications with the SRC-6 reconfigurable computer: Methodologies and analysis

Melissa C. Smith, Jeffery S. Vetter, Xuejun Liang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

27 Scopus citations

Abstract

Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software solution. Recently, the capacities of reconfigurable computing devices, like field programmable gate arrays, have risen to levels that make it possible to execute 64b floating-point operations, SRC Computers has designed the SRC-6 MAP station to blend the benefits of commodity processors with the benefits of reconfigurable computing. In this paper, we describe our effort to accelerate the performance of several scientific applications on the SRC-6. We describe our methodology, analysis, and results. Our early evaluation demonstrates that the SRC-6 provides a unique software stack that is applicable to many scientific solutions and our experiments reveal the performance benefits of the system.

Original languageEnglish
Title of host publicationProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Pages157b
DOIs
StatePublished - 2005
Event19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States
Duration: Apr 4 2005Apr 8 2005

Publication series

NameProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Volume2005

Conference

Conference19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Country/TerritoryUnited States
CityDenver, CO
Period04/4/0504/8/05

Keywords

  • Performance Analysis
  • Reconfigurable Computing
  • Scientific Applications

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