Abstract
A virtual zero-time VLSI sorting chip is described. The chip has a systolic array architecture and implements the sinking sort algorithm. The basic functional module of the systolic array is detailed, and development techniques employed as well as functional simulation and results are presented.
Original language | English |
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Pages (from-to) | 549-552 |
Number of pages | 4 |
Journal | Conference Proceedings - IEEE SOUTHEASTCON |
Volume | 2 |
State | Published - 1990 |
Event | IEEE Proceedings of Southeastcon '90 - Technologies Today and Tomorrow - New Orleans, LA, USA Duration: Apr 1 1990 → Apr 4 1990 |