A virtual zero-time, monolithic systolic sorting array

Research output: Contribution to journalConference articlepeer-review

Abstract

A virtual zero-time VLSI sorting chip is described. The chip has a systolic array architecture and implements the sinking sort algorithm. The basic functional module of the systolic array is detailed, and development techniques employed as well as functional simulation and results are presented.

Original languageEnglish
Pages (from-to)549-552
Number of pages4
JournalConference Proceedings - IEEE SOUTHEASTCON
Volume2
StatePublished - 1990
EventIEEE Proceedings of Southeastcon '90 - Technologies Today and Tomorrow - New Orleans, LA, USA
Duration: Apr 1 1990Apr 4 1990

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