A novel charge recycling approach to low-power circuit design

Chandradevi Ulaganathan, Charles L. Britton, Jeremy Holleman, Benjamin J. Blalock

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel charge-recycling scheme has been designed and implemented to demonstrate the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital logic. The proposed scheme uses capacitors to efficiently recover the ground-bound charge and to subsequently boost the capacitor voltage to power up the source circuit. This recycling methodology has been implemented on a 12-bit Gray-code counter within a 12-bit multi-channel Wilkinson ADC. The circuit has been designed in 0.5μm BiCMOS and in 90nm CMOS processes. SPICE simulation results reveal a 46-53% average reduction in the energy consumption of the counter. The total energy savings including the control generation aggregates to an average of 26-34%.

Original languageEnglish
Title of host publicationProceedings of the 19th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2012
PublisherIEEE Computer Society
Pages208-213
Number of pages6
ISBN (Print)9788362954438
StatePublished - 2012
Externally publishedYes
Event19th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2012 - Warsaw, Poland
Duration: May 24 2012May 26 2012

Publication series

NameProceedings of the 19th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2012

Conference

Conference19th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2012
Country/TerritoryPoland
CityWarsaw
Period05/24/1205/26/12

Keywords

  • Charge recycling
  • dynamic power supply
  • low-power
  • virtual power supply

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