Abstract
A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 μm process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.
Original language | English |
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Pages (from-to) | 374-378 |
Number of pages | 5 |
Journal | IEEE Transactions on Nuclear Science |
Volume | 44 |
Issue number | 3 PART 1 |
DOIs | |
State | Published - 1997 |
Funding
1 Research sponsored by the U.S. Department of Energy and performed at Oak Ridge National Laboratory, managed by Lockheed Martin Energy Research Corporation for the U.S. Department of Energy under Contract No. DE-AC05-960R22464.