A high resolution, extended temperature sigma delta ADC in 3.3V 0.μm SOS-CMOS

A ∑Δ modulator designed specifically for extended temperature applications is reported. The design is fabricated in a 3.3-V 0.5μm SOS-CMOS process and incorporates a 2-2 cascade architecture allowing operation as either a 2 ^nd- or 4 ^th-order modulator. Experimental data for both modulator configurations are presented including dynamic range (or effective resolution), signal-to-noise ratio and total harmonic distortion over a temperature range of 25°C to 225°C. The design obtains an effective resolution of ∼16 bits at 25°C and ∼12 bits at 225°C, both at a digital output rate of 2KS/S. Specific design details associated with high temperature operation are discussed including architectural issues, device sizing, and modulator noise. In addition, a digital decimation filter designed for use with the modulator and implemented in both software and in a field programmable gate array is summarized. This paper reports the first 4 ^th-order ∑Δ modulator fabricated in an SOI/SOS process and demonstrates the feasibility of high resolution data conversion at elevated temperatures.