TY - GEN
T1 - A High-Performance Design for Hierarchical Parallelism in the QMCPACK Monte Carlo code
AU - Luo, Ye
AU - Doak, Peter
AU - Kent, Paul
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - We introduce a new high-performance design for parallelism within the Quantum Monte Carlo code QMCPACK. We demonstrate that the new design is better able to exploit the hierarchical parallelism of heterogeneous architectures compared to the previous GPU implementation. The new version is able to achieve higher GPU occupancy via the new concept of crowds of Monte Carlo walkers, and by enabling more host CPU threads to effectively offload to the GPU. The higher performance is expected to be achieved independent of the underlying hardware, significantly improving developer productivity and reducing code maintenance costs. Scientific productivity is also improved with full support for fallback to CPU execution when GPU implementations are not available or CPU execution is more optimal.
AB - We introduce a new high-performance design for parallelism within the Quantum Monte Carlo code QMCPACK. We demonstrate that the new design is better able to exploit the hierarchical parallelism of heterogeneous architectures compared to the previous GPU implementation. The new version is able to achieve higher GPU occupancy via the new concept of crowds of Monte Carlo walkers, and by enabling more host CPU threads to effectively offload to the GPU. The higher performance is expected to be achieved independent of the underlying hardware, significantly improving developer productivity and reducing code maintenance costs. Scientific productivity is also improved with full support for fallback to CPU execution when GPU implementations are not available or CPU execution is more optimal.
KW - GPUs
KW - Heterogeneous computing
KW - Monte Carlo
UR - http://www.scopus.com/inward/record.url?scp=85147912311&partnerID=8YFLogxK
U2 - 10.1109/HiPar56574.2022.00008
DO - 10.1109/HiPar56574.2022.00008
M3 - Conference contribution
AN - SCOPUS:85147912311
T3 - Proceedings of HiPar 2022: 3rd Workshop on Hierarchical Parallelism for Exascale Computing, Held in conjunction with SC 2022: The International Conference for High Performance Computing, Networking, Storage and Analysis
SP - 22
EP - 27
BT - Proceedings of HiPar 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE/ACM International Workshop on Hierarchical Parallelism for Exascale Computing, HiPar 2022
Y2 - 13 November 2022 through 18 November 2022
ER -