A clock regenerator using two 2nd order sigma-delta modulators for wide range of dividing ratio

Seung Wuk Oh; Sang Ho Kim; Sang Soon Im; Yong Sung Ahn; Jin Ku Kang

doi:10.5573/JSTS.2012.12.1.10

A clock regenerator using two 2^nd order sigma-delta modulators for wide range of dividing ratio

Seung Wuk Oh
, Sang Ho Kim
, Sang Soon Im
, Yong Sung Ahn
, Jin Ku Kang

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents a clock regenerator using two 2n^d order σ-δ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different σ-δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 μm CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

Original language	English
Pages (from-to)	10-17
Number of pages	8
Journal	Journal of Semiconductor Technology and Science
Volume	12
Issue number	1
DOIs	https://doi.org/10.5573/JSTS.2012.12.1.10
State	Published - Mar 2012
Externally published	Yes

Keywords

Audio clock regenerator
Cycle time stamp (CTS)
High-definition multimedia interface (HDMI)
Multi-modulus divider (MMD)
Phase locked loop (PLL)
Sigma-delta modulator (SDM)
Transition minimized differential signaling (TMDS)

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abstract = "This paper presents a clock regenerator using two 2nd order σ-δ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different σ-δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 μm CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.",

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AU - Kim, Sang Ho

AU - Im, Sang Soon

AU - Ahn, Yong Sung

AU - Kang, Jin Ku

PY - 2012/3

Y1 - 2012/3

N2 - This paper presents a clock regenerator using two 2nd order σ-δ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different σ-δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 μm CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

AB - This paper presents a clock regenerator using two 2nd order σ-δ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different σ-δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 μm CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

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KW - Cycle time stamp (CTS)

KW - High-definition multimedia interface (HDMI)

KW - Multi-modulus divider (MMD)

KW - Phase locked loop (PLL)

KW - Sigma-delta modulator (SDM)

KW - Transition minimized differential signaling (TMDS)

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A clock regenerator using two 2^nd order sigma-delta modulators for wide range of dividing ratio

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Keywords

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