Abstract
This paper presents a clock regenerator using two 2nd order σ-δ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different σ-δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 μm CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.
Original language | English |
---|---|
Pages (from-to) | 10-17 |
Number of pages | 8 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 12 |
Issue number | 1 |
DOIs | |
State | Published - Mar 2012 |
Externally published | Yes |
Keywords
- Audio clock regenerator
- Cycle time stamp (CTS)
- High-definition multimedia interface (HDMI)
- Multi-modulus divider (MMD)
- Phase locked loop (PLL)
- Sigma-delta modulator (SDM)
- Transition minimized differential signaling (TMDS)